NJU6631A
PRELIMINARY
16-CHARACTER 1-LINE DOT MATRIX
LCD CONTROLLER DRIVER
s
GENERAL DESCRIPTION
The
NJU6631A
is a 1 Chip Dot Matrix LCD controller
driver for up to 16-character 1-line or 8-character 2-line
display.
It contains microprocessor interface circuits,
instruction decoder controller, character generator
ROM/RAM and common and segment drivers.
The bleeder resistance generates for LCD Bias
voltage internally.
The CR oscillator incorporates C and R, therefore no
external components for oscillation are required.
The microprocessor interface circuits which operate
2MHz frequency, can be connected directly to 4bit/8bit
microprocessor.
The character generator consists of 9,600 bits ROM
and 32 x 5 bits RAM. The standard version ROM is
coded with 192 characters including capital and small
letter fonts.
The 16-common and 40-segment drives up to 16-
character 1-line LCD panels which divided two common
electrode blocks.
The rectangle outlook is very applicable to COG or
Slim TCP.
s
PACKAGE OUTLINE
NJU6631ACH
s
FEATURES
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16-character 1-line Dot Matrix LCD Controller Driver
4/8 Bit Microprocessor Direct Interface
Display Data RAM
- 16 x 8 bits : Maximum 16-character 1-line Display
Character Generator ROM - 9,600 bits : 240 Characters for 5 x 8 Dots
Character Generator RAM - 32 x 5 bits : 4 Patterns(5 x 8 Dots)
Microprocessor can access to Display Data RAM and Character Generator RAM
High Voltage LCD Driver
: 16-common / 40-segment
Duty Ratio
: 1/16 Duty
Number of Maximum Display Characters : 16-character
Useful Instruction Set
Clear Display, Return Home, Display ON/OFF Cont, Cursor ON/OFF Cont, Display Blink,
Cursor Shift, Character Shift,
Common and Segment driver Location order Select Function(Pin configuration mode A / mode B)
Power On Initialize / Hardware Reset Function
Bleeder Resistance On-chip
Oscillation Circuit On-chip
Low Power Consumption
Operating Voltage --- +5V
Package Outline
--- Bumped Chip
C-MOS Technology
31.Mar,2000
Ver.1
NJU6631A
s
PAD LOCATION
31
74
Y
X
18
1
Chip Size
: 3.58mm x 1.68mm
Chip Center
: X=0um, Y=0um
Bump Material : Au
Bump Size
Bump Height
: 90um x 55um
: 17.5um TYP.
s
BLOCK DIAGRAM
RESET
Instruction
Reg.(IR)
Power On
Reset
8
Instruction 7 Address
Decoder(ID)
Counter(AC)
7
Display Data RAM
(DD RAM)
16x8bits
8
8
5
8
Character
Generator
ROM
(CG ROM)
9,600bits
5
Parallel to Serial
Converter
7
Timing
Gen.
16bit
Shift Reg.
Cursor Blink
Cont.
7
8
8
16
Common
Driver
Segment
Driver
OSC
1
OSC
2
CR
OSC
I/O Buffer
8
Data Reg.
(DR)
RS
R/W
E
DB
4
∼DB
7
DB
0
∼DB
3
V
SS
V
DD
R
1
16 COM
1
∼COM
16
Latch
4
4
5
Busy
Flag
Character
Generator
RAM
(CG RAM)
32x5bits
5
40
40
V
1
40bit
Shift Reg.
LCD Driver
R
1
V
2
R
1
V
3
R
1
V
4
R
1
V
5
40bit
SEG
1
∼SEG
40
NJU6631A
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PAD COORDINATES
PAD Name
Pin Configuration
Mode A
Mode B
Dummy1 Dummy1
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
5
V
5
V
5
V
5
V
5
V
5
V
3
V
3
V
2
V
2
RESET
RESET
RS
RS
R/W
R/W
E
E
DB
0
DB
0
DB
1
DB
1
DB
2
DB
2
Dummy2 Dummy2
DB
3
DB
3
DB
4
DB
4
DB
5
DB
5
DB
6
DB
6
DB
7
DB
7
COM
1
COM
9
COM
2
COM
10
COM
3
COM
11
COM
4
COM
12
COM
5
COM
13
COM
6
COM
14
COM
7
COM
15
COM
8
COM
16
Dummy3 Dummy3
Dummy4 Dummy4
SEG
1
SEG
40
SEG
2
SEG
39
SEG
3
SEG
38
SEG
4
SEG
37
SEG
5
SEG
36
SEG
6
SEG
35
SEG
7
SEG
34
SEG
8
SEG
33
SEG
9
SEG
32
SEG
10
SEG
31
SEG
11
SEG
30
Center
X=(um)
-1501
-1426
-1353
-1281
-1138
-1066
-993
-844
-614
-98
132
361
591
824
1091
1328
1406
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1459
1383
1313
1243
1173
1103
1033
963
893
823
753
683
613
Y=(um)
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-486
-416
-322
-253
-160
-13
57
127
197
267
337
407
477
690
690
690
690
690
690
690
690
690
690
690
690
690
Chip Size 3.58×1.68mm(Chip Center X=0um,Y=0um)
PAD Name
Center
PAD
Pin Configuration
No.
X=(um)
Y=(um)
Mode A
Mode B
44
SEG
12
SEG
29
543
690
45
SEG
13
SEG
28
473
690
46
SEG
14
SEG
27
403
690
47
SEG
15
SEG
26
333
690
48
SEG
16
SEG
25
263
690
49
SEG
17
SEG
24
193
690
50
SEG
18
SEG
23
123
690
51
SEG
19
SEG
22
53
690
52
SEG
20
SEG
21
-17
690
53
SEG
21
SEG
20
-87
690
54
SEG
22
SEG
19
-157
690
55
SEG
23
SEG
18
-227
690
56
SEG
24
SEG
17
-297
690
57
SEG
25
SEG
16
-367
690
58
SEG
26
SEG
15
-437
690
59
SEG
27
SEG
14
-507
690
60
SEG
28
SEG
13
-577
690
61
SEG
29
SEG
12
-647
690
62
SEG
30
SEG
11
-717
690
63
SEG
31
SEG
10
-787
690
64
SEG
32
SEG
9
-857
690
65
SEG
33
SEG
8
-927
690
66
SEG
34
SEG
7
-997
690
67
SEG
35
SEG
6
-1067
690
68
SEG
36
SEG
5
-1137
690
69
SEG
37
SEG
4
-1207
690
70
SEG
38
SEG
3
-1277
690
71
SEG
39
SEG
2
-1347
690
72
SEG
40
SEG
1
-1417
690
73
Dummy5 Dummy5
-1501
690
74
COM
16
COM
8
-1630
402
75
COM
15
COM
7
-1630
332
76
COM
14
COM
6
-1630
262
77
COM
13
COM
5
-1630
192
78
COM
12
COM
4
-1630
122
79
COM
11
COM
3
-1630
52
80
COM
10
COM
2
-1630
-18
81
COM
9
COM
1
-1630
-88
82
OSC
1
OSC
1
-1630
-230
83
OSC
2
OSC
2
-1630
-300
84
V
SS
V
SS
-1630
-370
85
V
SS
V
SS
-1630
-443
86
V
SS
V
SS
-1630
-515
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Note) Dummy1∼ Dummy5 are Dummy Pad.
NJU6631A
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TERMINAL DESCRIPTION
PAD No.
Pin Configuration
Mode A
Mode B
2,3,4
2,3,4
84,85,86 84,85,86
9,8,
9,8,
7,6,5
7,6,5
82
83
82
83
SYMBOL
V
DD
V
SS
V
2
,V
3
,
V
5
OSC
1
OSC
2
Power Source (+5V)
Power Source ( 0V)
LCD Driving Power Source
Oscillation Frequency Adjust Terminals. Normally Open.
(Oscillation C and R are incorporated, OSC Freq.=270kHz)
For external clock operation, the clock should be input on OSC1.
Register selection signal input
“0” : Instruction Register (Writing)
Busy Flag (Reading)
“1” : Data Register (Writing/Reading)
Read/Write selection signal input
“0” : Write, “1” : Read
Read/Write activation signal input
3-state Data Bus (Upper) to transfer the data between MPU and
NJU6631A
DB
7
is also used for the Busy flag reading.
3-state Data Bus (Lower) to transfer the data between MPU and
NJU6631A
These bus are not used in the 4-bit operation.
LCD Common driving signal Terminals
Common driver Location order Select as Shown in Table 4.
Pin configuration mode A : M0=0 / mode B : M0=1.
LCD Segment driving signal Terminals
Segment driver Location order Select as Shown in Table 4.
Pin configuration mode A : M0=0 / mode B : M0=1.
Reset Terminal. When the “L” level input over than 1.2ms to this
terminal the system will be reset. (f
OSC
=270kHz)
FUNCTION
11
11
RS
12
13
22∼19
12
13
22∼19
R/W
E
DB
7
∼DB
4
18∼14
18∼14
DB
3
∼DB
0
COM
1
∼COM
8
COM
9
∼COM
16
SEG
1
∼SEG
40
23∼30
81∼74
81∼74
23∼30
33∼72
72∼33
10
10
RESET
NJU6631A
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FUNCTIONAL DESCRIPTION
(1) Description for each blocks
(1-1) Register
The
NJU6631A
incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR).
The Register (IR) stores instruction codes such as “Clear Display” and “Return Home”, and address data for
Display Data RAM (DD RAM) and Character Generator RAM (CG RAM). The MPU can write the instruction
code and address data to the Register (IR), but it cannot read out from the Register (IR).
The Register (DR) is a temporary stored register, the data stored in the Register (DR) is written into the DD
RAM or CG RAM and read out from the DD RAM or CG RAM.
The data in the Register (DR) written by the MPU is transferred automatically to the DD RAM or CG RAM by
internal operation.
When the address data for the DD RAM or CG RAM is written into the Register (IR), the addressed data in
the DD RAM or CG RAM is transferred to the Register (DR). By the MPU read out the data in the Register
(DR), the data transmitting process is performed completely.
After reading the data in the Register (DR) by the MPU, the next address data in the DD RAM or CG RAM is
transferred automatically to the Register (DR) to provide for the next MPU reading.
These two registers are selected by the selection signal RS as shown below :
Table 1. shows register operation controlled by RS and R/W signals.
Table 1. Register Operation
RS
0
0
1
1
R/W
0
1
0
1
Selected Register
IR
DR
Operation
Write
Read busy flag (DB
7
) and address counter (DB
0
∼DB
6
)
Write (DR to DD RAM or CG RAM)
Read (DD RAM or CG RAM to DR)
(1-2) Busy Flag (BF)
When the internal circuits are in the operation mode, the busy flag is "1", and any instruction reading is
inhibited.
The busy flag (BF) is output at DB
7
when RS="0" and R/W="1" as shown in table 1.
The next instruction should be written after busy flag (BF) goes to "0".
(1-3) Address Counter (AC)
The address Counter (AC) addressing the DD RAM and CG RAM.
When the address setting instruction is written into the Register (IR), the address information is transferred
from Register (IR) to counter (AC). The selection of either the DD RAM or CG RAM is also determined by this
instruction.
After writing (or reading) the display data to (or from) the DD RAM or CG RAM, the Counter (AC)
increments (or decrements) automatically.
The address data in the Counter (AC) is output from DB
6
∼DB
0
when RS="0" and R/W="1" as shown in Table
1.
(1-4) Display Data RAM (DD RAM)
The display data RAM (DD RAM) consists of 16 x 8 bits, stores up to 16-character display data represented
in 8-bit code.
The DD RAM address data set in the address Counter (AC) is represented in Hexadecimal.
Higher order bit
AC
AC
6
AC
5
AC
4
AC
3
Lower order bit
AC
2
AC
1
AC
0
(Example) DD RAM address “08”
0
0
0
1
0
0
8
0
0
Hexadecimal
Hexadecimal
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