NM24Wxx 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
Connection Diagrams
Dual-In-Line Package (N), SO Package (M8), and TSSOP Package (MT8)
A0
A1
A2
VSS
1
2
8
7
VCC
WP
SCL
SDA
NC
A1
A2
VSS
1
2
8
7
VCC
WP
SCL
SDA
NC
NC
A2
VSS
1
2
8
7
6
5
VCC
WP
SCL
SDA
NC
NC
NC
VSS
1
2
8
7
6
5
VCC
WP
SCL
SDA
NM24W02
3
4
6
5
3
4
NM24W04
6
5
NM24W08
3
4
NM24W16
3
4
DS500074-2
DS500074-3
DS500074-4
DS500074-18
Top View
See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
A0,A1,A2
V
SS
SDA
SCL
WP
V
CC
NC
Device Address Inputs
Ground
Data I/O
Clock Input
Write Protect
Power Supply
No Connect
Ordering Information
NM
24
W
XX
LZ
E
XX
Package
Letter
N
M8
MT8
None
E
V
Blank
L
LZ
02
04
08
16
W
Interface
24
NM
Description
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
0 to 70°C
-40 to +85°C
-40°C to +125°C
4.5V to 5.5V
2.7V to 4.5V
2.7V to 4.5V and
<1µA Standby Current
2K
4K
8K
16K
Total Array Write Protect
IIC
Fairchild Non-Volatile
Memory
Temp. Range
Voltage Operating Range
Density
2
NM24Wxx Rev. C.2
www.fairchildsemi.com
NM24Wxx 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
Product Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 seconds)
ESD Rating
–65°C to +150°C
6.5V to –0.3V
+300°C
2000V min.
Operating Conditions
Ambient Operating Temperature
NM24Wxx
NM24WxxE
NM24WxxV
Positive Power Supply
NM24Wxx
NM24WxxL
NM24WxxLZ
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4.5V to 5.5V
2.7V to 4.5V
2.7V to 4.5V
Standard V
CC
(4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
I
CCA
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL
Active Power Supply Current
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
I
OL
= 3 mA
f
SCL
= 100 kHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
–0.3
V
CC
x 0.7
Limits
Typ
(Note 1)
0.2
10
0.1
0.1
Units
Max
1.0
50
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
mA
µA
µA
µA
V
V
V
Low V
CC
(2.7V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
I
CCA
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL
Active Power Supply Current
Standby Current for L
Standby Current for LZ
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
I
OL
= 3 mA
f
SCL
= 100 kHz
V
IN
= GND or V
CC
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
–0.3
V
CC
x 0.7
Limits
Typ
(Note 1)
0.2
1
0.1
0.1
0.1
Units
Max
1.0
10
1
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
mA
µA
µA
µA
µA
V
V
V
Capacitance
T
A
= +25°C, f = 100/400 KHz, V
CC
= 5V
(Note 2)
Symbol
C
I/O
C
IN
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
Conditions
V
I/O
= 0V
V
IN
= 0V
Max
8
6
Units
pF
pF
Note 1:
Typical values are T
A
= 25°C and nominal supply voltage (5V).
Note 2:
This parameter is periodically sampled and not 100% tested.
3
NM24Wxx Rev. C.2
www.fairchildsemi.com
NM24Wxx 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
AC Conditions of Test
Input Pulse Levels
Input Rise and Fall Times
Input & Output Timing Levels
Output Load
V
CC
x 0.1 to V
CC
x 0.9
10 ns
V
CC
x 0.5
1 TTL Gate and C
L
= 100 pF
Read and Write Cycle Limits (Standard and Low V
CC
Range 2.7V - 4.5V)
Symbol
f
SCL
T
I
Parameter
SCL Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
IN
Pulse width)
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time - NM24Wxx
- NM24WxxL, NM24WxxLZ
100 KHz
Min
Max
100
100
0.3
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
300
10
15
3.5
400 KHz
Min
Max
400
50
0.1
1.3
0.6
1.5
0.6
0.6
0
100
0.3
300
0.6
50
10
15
0.9
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
WR
(Note 3)
Note 3:
The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24Wxx bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
4
NM24Wxx Rev. C.2
www.fairchildsemi.com
NM24Wxx 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
Bus Timing
tF
tHIGH
tLOW
SCL
tLOW
tR
SDA
SDA
OUT
Background Information (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional com-
munication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condi-
tion.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROMs, etc., a devce type identifier string must
follow the START condition. For EEPROMs, this 4-bit string is
1010 and is the first 4 bits in the slave address.
As shown below, the EEPROMs on the IIC bus may be configured
in any manner required, and for the Standard IIC protocol, the total
memory addressed can not exceed 16K (16,384 bits). EEPROM
memory address programming is controlled by 2 methods:
• Hardware configuring the A0, A1, and A2 pins (Device
Address pins) with pull-up or pull-down to resistors.
All
unused pins must be grounded
(tied to V
SS
).
• Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]—[DEVICE ADDRESS]—[PAGE BLOCK
ADDRESS]—[BYTE ADDRESS]
,,
tSU:STA
tHD:STA
IN
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tDH
tAA
DS500074-5
DEFINITIONS
WORD
PAGE
8 bits of data
16 sequential addresses (one byte
each) that may be programmed
during a 'Page Write' programming
cycle
2,048 (2K) bits organized into 16
pages of addressable memory. (8
bits) x (16 bytes) x (16 pages) = 2,048
bits
Any IIC device CONTROLLING the
transfer of data (such as a micropro-
cessor)
Device being controlled (EEPROMs
are always considered Slaves)
Device currently SENDING data on
the bus (may be either a Master or
Slave).
Device currently receiving data on the
bus (Master or Slave)
PAGE BLOCK
MASTER
SLAVE
TRANSMITTER
RECEIVER
Example of 16K of Memory on 2-Wire Bus
VCC
VCC
SDA
SCL
VCC
VCC
VCC
VCC
NM24W02
A0 A1 A2 VSS
NM24W02
A0 A1 A2 VSS
NM24W04
A0 A1 A2 VSS
NM24W08
A0 A1 A2 VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
DS500074-6
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF.
Specific timing and addressing considerations are described in greater detail in the following sections.
卡巴斯基的安全研究人员称其发现了如何攻击Intel微处理器的远程攻击代码，据传，这一代码可以通过TCP/IP包和JavaScript代码到达用户系统。 目前受影响的系统包括Windows XP，Vista，Windows Server 2003，Windows Server 2008，Linux甚至是BSD和Mac。但所幸大多数错误可以由Intel和BIOS厂商联合进行修复。 卡...[详细]
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