IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
3.3V/2.5V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
FEATURES:
• Phase-lock loop clock distribution for high performance clock
tree applications
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Operates at 3.3V/2.5V V
CC
• Spread Spectrum Compatible
• Operating frequency up to 200MHz
• Compatible with Motorola MPC9352
• Available in 32-pin TQFP package
IDT5V9352
DESCRIPTION:
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver
targeted for high performance clock tree applications. It uses a PLL to
precisely align, in both frequency and phase. The 5V9352 operates at 2.5V
and 3.3V.
The 5V9352 features three banks of individually configurable outputs.
The banks are configured with five, four, and two outputs. The internal
divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1.
The output frequency relationship is controlled by the f
SEL
frequency
control pins. The f
SEL
pins, as well as other inputs, are LVCMOS/LVTTL
compatible inputs
Unlike many products containing PLLs, the 5V9352 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the 5V9352 requires a stabilization
time to achieve phase lock of the feedback signal to the reference signal.
This stabilization time is required, following power up and application of a
fixed-frequency, fixed-phase signal at REFCLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for test purposes by setting the
PLL_EN
to high.
The 5V9352 is available in Industrial temperature range (-40°C to
+85°C).
FUNCTIONAL BLOCK DIAGRAM
BANK A
CCLK
REFCLK
REF
PLL
FBIN
FB
÷2
Q
A
3
Q
A
0
1
÷2
1
÷6
1
Q
A
1
0
0
÷4
0
Q
A
2
VCO
PLL_En
Q
A
4
BANK B
Q
B
0
VCO_
SEL
1
Q
B
1
f
SELA
0
Q
B
2
Q
B
3
f
SELB
BANK C
1
f
SELC
0
Q
C
0
Q
C
1
MR/OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2003
Integrated Device Technology, Inc.
AUGUST 2003
DSC 5973/18
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND
Q
C
1
Q
C
0
GND
Q
B
2
Q
B
3
V
CC
V
CC
32
VCO_
SEL
f
SELC
f
SELB
f
SELA
MR/OE
REFCLK
GND
FBIN
1
2
3
4
5
6
7
8
9
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
Q
B
1
Q
B
0
V
CC
V
CC
Q
A
4
Q
A
3
GND
10
11
12
13
14
15
16
PLL_En
Q
A
0
Q
A
1
GND
Q
A
2
V
CC
V
CCA
TQFP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
V
I
I
IN
I
OUT
T
STG
Rating
Supply Voltage Range
Input Voltage Range
Input Current
DC Output Current
Storage Temperature Range
Max.
–0.3 to +3.6
–0.3 to V
CC
+0.3
±20
±50
–65 to +125
Unit
V
V
mA
mA
°C
CAPACITANCE
Parameter
C
IN
C
PD
Description
Input Capacitance
Power Dissipation
Capacitance
Min.
Typ.
4
10
Max.
Unit
pF
pF
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress rating only, and functional
operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
LOGIC DIAGRAM
(1,2)
R
F
V
CC
C
F
10nF
V
CCA
GENERAL SPECIFICATIONS
Symbol
V
TT
HBM
LU
Description
Output Termination Voltage
ESD Protection (human body model)
Latch-Up Immunity
2000
200
Min.
Typ.
V
CC
/2
Max. Unit
V
V
mA
NOTES:
1. IDT5V9352 requires an external RC filter for the analog power supply pin V
CCA
.
2. For V
CC
= 2.5V, R
F
= 9-10Ω, C
F
= 22µF.
For V
CC
= 3.3V, R
F
= 5-15Ω, C
F
= 22µF.
33...100nF
V
CC
2
V
CC
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLES
f
SELA
0
1
Q
A
n
÷4
÷6
f
SELB
0
1
Q
B
n
÷4
÷2
f
SELC
0
1
Q
C
n
÷2
÷4
Control Pin
VCO_
SEL
MR/OE
PLL_En
Logic 0
fVCO
Output Enable
Enable PLL
fVCO / 2
Outputs disable (high-impedance state) and
reset of the device.
Disable PLL
Logic 1
NOTE:
1. IDT5V9352 requires reset at power up and after any loss of PLL lock. Length of reset
pulse should be greater than two REF CLK cycles (REFCLK).
PIN DESCRIPTION
Terminal
Name
REFCLK
FBIN
V
CCA
GND
VCO_
SEL
MR/OE
Q
A (0:4)
Q
B (0:3)
Q
C (0:1)
V
CC
PLL_EN
f
SEL(C:A)
No.
6
8
10
7, 13, 17, 24,
28, 29
1
5
12, 14, 15,
18, 19
22, 23, 26, 27
30, 31
11, 16, 20, 21,
25, 32
9
2, 3, 4
I
I
PLL enable input. When set LOW, PLL is enabled. When set HIGH, PLL is disabled.
Frequency control pin
PWR
Positive power supply for I/O and core
O
Clock outputs. These outputs provide low skew copies of REFCLK or can be at different frequencies than REFCLK.
I
I
Allows for the choice of two VCO ranges to optimize PLL stability and jitter performance
Allows the user to force the outputs into HIGH impedence for board level test
Type
I
I
PWR
Ground
Description
Reference clock input
Feedback input.
Analog power supply
Negative power supply
DC ELECTRICAL CHARACTERISTICS
T
A
= –40°C to +85°C, V
CC
= 3.3V ± 5%
Parameter
V
IH
V
IL
V
OH
V
OL
Z
OUT
I
I
I
CC
I
CCA
Description
Input HIGH Level
Input LOW Level
HIGH Level Output Voltage
LOW Level Output Voltage
Output Impedance
Input Current
(2)
Maximum Quiescent Supply Current
(3)
PLL Supply Current
V
I
= V
CC
or GND
All V
CC
pins
V
CCA
pin
3
I
OH
= –24mA
I
OL
= 12mA
I
OL
= 24mA
14 - 17
±200
1
5
2.4
0.3
0.55
Ω
µA
mA
mA
Test Conditions
Min.
2
Typ.
(1)
Max.
V
CC +
0.3
0.8
Unit
V
V
V
V
NOTES:
1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.
2. Inputs have pull-down resistors affecting the input current.
3. Icc is the DC current consumption of the device with all outputs open in high-impedance state and the inputs in its default state or open.
3
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS
T
A
= –40°C to +85°C, V
CC
= 3.3V ± 5%
Symbol
Description
÷4
feedback
÷6
feedback
REF
Reference CLK input in PLL mode
(1)
Reference CLK input in PLL bypass mode
(2)
d
H
t
R
, t
F
Input clock duty cycle
Maximum input rise and fall times, 0.8V to 2V
25
÷8
feedback
÷12
feedback
Min.
50
33.3
25
16.67
Max.
100
66.6
50
33.3
250
75
1
%
ns
MHz
Unit
NOTES:
1. PLL mode requires
PLL_EN
= 0 to enable the PLL and zero delay operation.
2. In PLL bypass mode, the IDT5V9352 divides the input reference clock.
4
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(1)
T
A
= –40°C to +85°C, V
CC
= 3.3V ± 5%
Symbol
t
R,
t
F
t
SK(O)
Characteristic
Output Rise/Fall Time
Output to Output Skew
Test Conditions
0.55V to 2.4V
All Outputs, any frequency
within Q
A
output bank
within Q
B
output bank
within Q
C
output bank
f
VCO
PLL VCO Lock Range
(2)
÷2
output
÷4
output
f
MAX
Maximum Output Frequency
÷6
output
÷8
output
÷12
output
t
PW
t
PD
t
PLZ
t
PHZ
t
PZL
t
PZH
t
J
Output Duty Cycle
REFCLK to FBIN Delay
PLL Locked
Output Disable Time
MR/OE (LOW-HIGH) to any Q
Output Enable Time
MR/OE (HIGH-LOW) to any Q
Output frequencies mixed
Cycle-to-Cycle Jitter
Outputs in any
÷4
and
÷6
combination
All outputs same frequency
Output frequencies mixed
t
J(PER)
Period Jitter
Outputs in any
÷4
and
÷6
combination
All outputs same frequency
÷4
feedback divider RMS (1σ)
t
J(
φ
)
I/O Phase Jitter
÷6
feedback divider RMS (1σ)
÷8
feedback divider RMS (1σ)
÷12
feedback divider RMS (1σ)
÷4
feedback
BW
PLL Closed Loop Bandwidth
÷6
feedback
÷8
feedback
÷12
feedback
t
LOCK
Maximum PLL Lock Time
NOTES:
1. AC characteristics apply for parallel output termination of 50Ω to V
TT
.
2. The input frequency on CCLK must match the VCO frequency range divided by the feedback divide ratio FB: freq. = fvco
÷
FB.
Min.
0.1
Typ.
Max.
1
200
200
100
100
Unit
ns
ps
200
100
50
33.3
25
16.67
47
f
REF
< 40MHz
f
REF
> 40MHz, PLL locked
-200
-50
50
400
200
100
66.6
50
33.3
53
+150
+150
8
10
400
250
100
200
150
75
15
20
18-20
25
3 - 10
1.5 - 6
1 - 3.5
0.5 - 2
10
MHz
MHz
%
ps
ns
ns
ps
ps
ps
MHz
ms
5
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