DATA SHEET
512MB Registered SDRAM DIMM
EBS51RC4ACFC (64M words
×
72 bits, 1 bank)
Description
The EBS51RC4ACFC is 64M words
×
72 bits, 1 bank
Synchronous Dynamic RAM Registered Module,
mounted 18 pieces of 256M bits SDRAM sealed in
TSOP package. This module provides high density
and large quantities of memory in a small space
without utilizing the surface mounting technology.
Decoupling capacitors are mounted on power supply
line for noise reduction.
Features
•
Fully compatible with 8 bytes DIMM: JEDEC
standard outline
•
168-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm (1.20inch)
Lead pitch: 1.27mm
•
3.3V power supply
•
Clock frequency: 133MHz (max.)
•
LVTTL interface
•
Data bus width:
×
72 ECC
•
Single pulsed /RAS
•
4 Banks can operates simultaneously and
independently
•
Burst read/write operation and burst read/single write
operation capability
•
Programmable burst length (BL): 1, 2, 4, 8
•
2 variations of burst sequence
Sequential
Interleave
•
Programmable /CAS latency (CL): 2, 3
•
Registered inputs with one clock delay
•
Byte control by DQMB
•
Refresh cycles: 8192 refresh cycles/64ms
•
2 variations of refresh
Auto refresh
Self refresh
•
1 piece of PLL clock driver, 3 pieces of register driver
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (SPD) on PCB.
Document No. E0108E30 (Ver. 3.0)
Date Published May 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2001-2002
EBS51RC4ACFC
Ordering Information
Part number
EBS51RC4ACFC-7A
EBS51RC4ACFC-75*
Clock frequency
MHz (max.)
133
133
/CAS latency
2, 3
3
Package
168-pin DIMM
Contact pad
Gold
Mounted devices
EDS2504ACTA
Note: 100MHz operation at /CAS latency = 2.
Pin Configurations
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin name
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VDD
/WE
DQMB0
DQMB1
/CS0
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin name
VSS
NC
/CS2
DQMB2
DQMB3
NC
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
Pin No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
Pin name
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VDD
/CAS
DQMB4
DQMB5
NC
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Pin name
VSS
CKE0
NC
DQMB6
DQMB7
NC
VDD
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
NC
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
Data Sheet E0108E30 (Ver. 3.0)
2
EBS51RC4ACFC
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
Pin name
NC
VSS
A0
A2
A4
A6
A8
A10 (AP)
BA1
VDD
VDD
CLK0
Pin No.
73
74
75
76
77
78
79
80
81
82
83
84
Pin name
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
NC
SDA
SCL
VDD
Pin No.
115
116
117
118
119
120
121
122
123
124
125
126
Pin name
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CLK1
A12
Pin No.
157
158
159
160
161
162
163
164
165
166
167
168
Pin name
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
SA0
SA1
SA2
VDD
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/CS0, /CS2
/RAS
/CAS
/WE
DQMB0 to DQMB7
CLK0 to CLK3
CKE0
REGE*
SDA
SCL
SA0 to SA2
VDD
VSS
NC
1
Function
Address input
Row address
A0 to A12
Column address A0 to A9, A11
Bank select address
Data input/output
Check bit (Data input/output)
Chip select input
Row enable (/RAS) input
Column enable (/CAS) input
Write enable input
Byte data mask
Clock input
Clock enable input
Register/Buffer enable
Data input/output for serial PD
Clock input for serial PD
Serial address input
Primary positive power supply
Ground
No connection
Note: 1. REGE
≥
VIH: Register mode.
REGE
≤
VIL: Buffer mode.
Data Sheet E0108E30 (Ver. 3.0)
3
EBS51RC4ACFC
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
6
7
8
9
1
Function described
Number of bytes used by module
manufacturer
Total SPD memory size
Memory type
Number of row addresses bits
Number of column addresses bits
Number of banks
Module data width
Module data width (continued)
Module interface signal levels
SDRAM cycle time
(highest /CAS latency)
7.5ns
SDRAM access from Clock
(highest /CAS latency)
5.4ns
Module configuration type
Refresh rate/type
SDRAM width
Error checking SDRAM width
SDRAM device attributes:
minimum clock delay for back-to-
back random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes: number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM device attributes
SDRAM device attributes: General
SDRAM cycle time
(2nd highest /CAS latency)
(-7A) 7.5ns
(-75) 10ns
SDRAM access from Clock
(2nd highest /CAS latency)
(-7A)5.4ns
(-75) 6ns
SDRAM cycle time
(3rd highest /CAS latency)
Undefined
SDRAM access from Clock
(3rd highest /CAS latency)
Undefined
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
80H
08H
04H
0DH
0BH
01H
48H
00H
01H
75H
Comments
128
256 byte
SDRAM
13
11
1
72 bit
0 (+)
LVTTL
CL = 3*
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
1
1
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
0
0
0
0
54H
02H
82H
04H
04H
01H
0FH
04H
06H
01H
01H
1FH
0EH
75H
A0H
54H
60H
00H
ECC
Normal
(7.8125µs)
Self refresh
64M
×
4
×
4
1 CLK
1, 2, 4, 8
4
2, 3
0
0
Registered
VDD ± 10%
CL = 2*
5
24
25
26
0
0
0
0
0
0
0
0
00H
Data Sheet E0108E30 (Ver. 3.0)
4
EBS51RC4ACFC
Byte No.
27
Function described
Minimum row precharge time
(-7A)
(-75)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
×
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
×
1
1
1
0
0
1
1
0
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
×
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
1
1
1
0
×
0
0
1
1
1
1
0
1
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
0
0
0
1
1
1
0
×
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
0
1
0
0
0
1
1
1
1
0
×
1
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
×
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
0
0
1
0
1
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
1
0
0
×
1
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0FH
14H
0FH
0FH
14H
2DH
80H
15H
08H
15H
08H
00H
3CH
43H
00H
12H
B7H
FFH
7FH
FEH
00H
××
45H
42H
53H
35H
31H
52H
43H
34H
41H
43H
46H
43H
2DH
37H
41H
35H
20H
Comments
15ns
20ns
15ns
15ns
20ns
45ns
1 bank
512M byte
1.5ns*
5
0.8ns*
5
1.5ns*
5
0.8ns*
5
Future use
60ns
67.5ns
Future use
Rev. 1.2
183
255
Continuation code
Elpida Memory
28
29
Row active to row active min
/RAS to /CAS delay min
(-7A)
(-75)
30
31
32
33
34
35
36 to 40
41
Minimum /RAS pulse width
Density of each bank on module
Address and command signal input
setup time
Address and command signal input
hold time
Data signal input setup time
Data signal input hold time
Superset information
Minimum bank Cycle
(-7A)
(-75)
42 to 61
62
63
Superset information
SPD data revision code
Checksum for bytes 0 to 62
(-7A)
(-75)
64 to 65
66
67 to 71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
(-7A)
(-75)
*
2
(ASCII-8bit code)
E
B
S
5
1
R
C
4
A
C
F
C
—
7
A
5
(Space)
88
Manufacturer’s part number
Data Sheet E0108E30 (Ver. 3.0)
5
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