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PRELIMINARY DATA SHEET

512MB DDR SDRAM SO DIMM

EBD52UC8AKDA

(64M words

×

64 bits, 2 Ranks)

Description

The EBD52UC8AKDA is 64M words

×

64 bits, 2 ranks

Double Data Rate (DDR) SDRAM Small Outline Dual

In-line Memory Module, mounting 16 pieces of 256M

bits DDR SDRAM sealed in TCP package. Read and

write operations are performed at the cross points of

the CK and the /CK. This high-speed data transfer is

realized by the 2 bits prefetch-pipelined architecture.

Data strobe (DQS) both for read and write are available

for high speed and reliable data bus design. By setting

extended mode register, the on-chip Delay Locked

Loop (DLL) can be set enable or disable. This module

provides high density mounting without utilizing surface

mount technology. Decoupling capacitors are mounted

beside each TCP on the module board.

Note: Do not push the cover or drop the modules in

order to avoid mechanical defects, which may

result in electrical defects.

Features

•

200-pin socket type small outline dual in line memory

module (SO DIMM)



PCB height: 31.75mm



Lead pitch: 0.6mm

•

2.5V power supply

•

Data rate: 333Mbps/266Mbps (max.)

•

2.5 V (SSTL_2 compatible) I/O

•

Double Data Rate architecture; two data transfers per

clock cycle

•

Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

•

Data inputs, outputs and DM are synchronized with

DQS

•

4 internal banks for concurrent operation

(Component)

•

DQS is edge aligned with data for READs; center

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

referenced to both edges of DQS

•

Data mask (DM) for write data

•

Auto precharge option for each burst access

•

Programmable burst length: 2, 4, 8

•

Programmable /CAS latency (CL): 2, 2.5

•

Refresh cycles: (8192 refresh cycles /64ms)



7.8µs maximum average periodic refresh interval

•

2 variations of refresh



Auto refresh



Self refresh

Document No. E0367E20 (Ver. 2.0)

Date Published March 2003 (K) Japan

URL: http://www.elpida.com

Elpida

Memory , Inc. 2003

EBD52UC8AKDA

Ordering Information

Data rate

Mbps (max.)

333

266

Component

JEDEC speed bin

(CL-tRCD-tRP)

DDR333B (2.5-3-3)

DDR266A (2-3-3)

DDR266B (2.5-3-3)

Contact

pad

Mounted devices

256M bits DDR SDRAM TCP*

1

Part number

EBD52UC8AKDA-6B

EBD52UC8AKDA-7A

EBD52UC8AKDA-7B

Package

200-pin SO DIMM Gold

Note:

Please refer to 256Mb DDR TSOP product datasheet for electrical characteristics.

Pin Configurations

Front side

1 pin

39 pin 41 pin

199 pin

2 pin

40 pin 42 pin

Back side

200 pin

Pin No.

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

Pin name

VREF

VSS

DQ0

DQ1

VDD

DQS0

DQ2

VSS

DQ3

DQ8

VDD

DQ9

DQS1

VSS

DQ10

DQ11

VDD

CK0

/CK0

VSS

DQ16

DQ17

VDD

DQS2

DQ18

Pin No.

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

Pin name

VSS

DQ19

DQ24

VDD

DQ25

DQS3

VSS

DQ26

DQ27

VDD

NC

VSS

NC

VDD

NC

VSS

CK2

/CK2

VDD

CKE1

NC

A12

Pin No.

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

Pin name

VREF

VSS

DQ4

DQ5

VDD

DM0

DQ6

VSS

DQ7

DQ12

VDD

DQ13

DM1

VSS

DQ14

DQ15

VDD

VSS

DQ20

DQ21

VDD

DM2

DQ22

Pin No.

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

Pin name

VSS

DQ23

DQ28

VDD

DQ29

DM3

VSS

DQ30

DQ31

VDD

NC

VSS

NC

VDD

NC

VSS

VDD

CKE0

NC

A11

Preliminary Data Sheet E0367E20 (Ver. 2.0)

2

EBD52UC8AKDA

Pin No.

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

Pin name

A9

VSS

A7

A5

A3

A1

VDD

A10/AP

BA0

/WE

/CS0

NC

VSS

DQ32

DQ33

VDD

DQS4

DQ34

VSS

DQ35

DQ40

VDD

DQ41

DQS5

VSS

Pin No.

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

Pin name

DQ42

DQ43

VDD

VSS

DQ48

DQ49

VDD

DQS6

DQ50

VSS

DQ51

DQ56

VDD

DQ57

DQS7

VSS

DQ58

DQ59

VDD

SDA

SCL

VDDSPD

VDDID

Pin No.

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

Pin name

A8

VSS

A6

A4

A2

A0

VDD

BA1

/RAS

/CAS

/CS1

NC

VSS

DQ36

DQ37

VDD

DM4

DQ38

VSS

DQ39

DQ44

VDD

DQ45

DM5

VSS

Pin No.

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

Pin name

DQ46

DQ47

VDD

/CK1

CK1

VSS

DQ52

DQ53

VDD

DM6

DQ54

VSS

DQ55

DQ60

VDD

DQ61

DM7

VSS

DQ62

DQ63

VDD

SA0

SA1

SA2

NC

Preliminary Data Sheet E0367E20 (Ver. 2.0)

3

EBD52UC8AKDA

Pin Description

Pin name

A0 to A12

BA0, BA1

DQ0 to DQ63

/RAS

/CAS

/WE

/CS0, /CS1

CKE0, CKE1

CK0 to CK2

/CK0 to /CK2

DQS0 to DQS7

DM0 to DM7

SCL

SDA

SA0 to SA2

VDD

VDDSPD

VREF

VSS

VDDID

NC

Function

Address input

Row address

Column address

Data input/output

Row address strobe command

Column address strobe command

Write enable

Chip select

Clock enable

Clock input

Differential clock input

Input and output data strobe

Input mask

Clock input for serial PD

Data input/output for serial PD

Serial address input

Power for internal circuit

Power for serial EEPROM

Input reference voltage

Ground

VDD identification flag

No connection

A0 to A12

A0 to A9

Bank select address

Preliminary Data Sheet E0367E20 (Ver. 2.0)

4

EBD52UC8AKDA

Serial PD Matrix

Byte No. Function described

0

1

2

3

4

5

6

7

8

9

Number of bytes utilized by module

manufacturer

Total number of bytes in serial PD

device

Memory type

Number of row address

Number of column address

Number of DIMM ranks

Module data width

Module data width continuation

DDR SDRAM cycle time, CL = X

-6B

-7A, -7B

10

SDRAM access from clock (tAC)

-6B

-7A, -7B

11

12

13

14

15

16

17

18

19

20

21

22

23

DIMM configuration type

Refresh rate/type

Primary SDRAM width

Error checking SDRAM width

SDRAM device attributes:

Minimum clock delay back-to-back

column access

SDRAM device attributes:

Burst length supported

SDRAM device attributes: Number of

banks on SDRAM device

SDRAM device attributes: /CS latency

SDRAM device attributes: /WE latency

SDRAM module attributes

SDRAM device attributes: General

Minimum clock cycle time at

CL = X –0.5

-6B, -7A

-7B

24

Maximum data access time (tAC) from

clock at CL = X –0.5

-6B

-7A, -7B

25 to 26

27

Minimum row precharge time (tRP)

-6B

-7A, -7B

28

Bit7

1

0

Bit6

0

1

0

1

0

1

0

1

0

1

0

Bit5 Bit4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bit3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bit2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bit1 Bit0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Hex value

80H

08H

07H

0DH

0AH

02H

40H

00H

04H

60H

75H

70H

75H

00H

82H

08H

00H

01H

0EH

04H

0CH

01H

02H

20H

C0H

75H

A0H

70H

75H

00H

48H

50H

30H

3CH

18ns

20ns

12ns

15ns

0.7ns

*1

0.75ns*

1

0.7ns

*1

0.75ns

*1

None

7.8µs

Self refresh

×

8

Not used

1 CLK

2,4,8

4

2, 2.5

0

1

Unbuffered

VDD ± 0.2V

CL = 2*

1

Comments

128 bytes

256 bytes

DDR SDRAM

13

10

2

64 bits

0

SSTL2

CL = 2.5*

1

Voltage interface level of this assembly 0

0

1

0

SDRAM device attributes: /CAS latency 0

0

1

0

1

0

Minimum row active to row active delay

0

(tRRD)

-6B

-7A, -7B

0

Preliminary Data Sheet E0367E20 (Ver. 2.0)

5

	EBD52UC8AKDA	EBD52UC8AKDA-6B	EBD52UC8AKDA-7B	EBD52UC8AKDA-7A
描述	512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)	512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)	512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)	512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)
是否Rohs认证	-	不符合	不符合	不符合
厂商名称	-	ELPIDA	ELPIDA	ELPIDA
零件包装代码	-	MODULE	MODULE	MODULE
包装说明	-	DIMM, DIMM200,24	DIMM, DIMM200,24	DIMM, DIMM200,24
针数	-	200	200	200
Reach Compliance Code	-	unknow	unknow	unknow
ECCN代码	-	EAR99	EAR99	EAR99
访问模式	-	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
最长访问时间	-	0.7 ns	0.75 ns	0.75 ns
其他特性	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	-	167 MHz	133 MHz	133 MHz
I/O 类型	-	COMMON	COMMON	COMMON
JESD-30 代码	-	R-XDMA-N200	R-XDMA-N200	R-XDMA-N200
JESD-609代码	-	e0	e0	e0
内存密度	-	4294967296 bi	4294967296 bi	4294967296 bi
内存集成电路类型	-	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
内存宽度	-	64	64	64
功能数量	-	1	1	1
端口数量	-	1	1	1
端子数量	-	200	200	200
字数	-	67108864 words	67108864 words	67108864 words
字数代码	-	64000000	64000000	64000000
工作模式	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	-	70 °C	70 °C	70 °C
组织	-	64MX64	64MX64	64MX64
输出特性	-	3-STATE	3-STATE	3-STATE
封装主体材料	-	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	-	DIMM	DIMM	DIMM
封装等效代码	-	DIMM200,24	DIMM200,24	DIMM200,24
封装形状	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	-	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	-	235	235	235
电源	-	2.5 V	2.5 V	2.5 V
认证状态	-	Not Qualified	Not Qualified	Not Qualified
刷新周期	-	8192	8192	8192
自我刷新	-	YES	YES	YES
最大压摆率	-	3.24 mA	2.8 mA	2.8 mA
最大供电电压 (Vsup)	-	2.7 V	2.7 V	2.7 V
最小供电电压 (Vsup)	-	2.3 V	2.3 V	2.3 V
标称供电电压 (Vsup)	-	2.5 V	2.5 V	2.5 V
表面贴装	-	NO	NO	NO
技术	-	CMOS	CMOS	CMOS
温度等级	-	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	-	NO LEAD	NO LEAD	NO LEAD
端子节距	-	0.6 mm	0.6 mm	0.6 mm
端子位置	-	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED

EBD52UC8AKDA

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