PRELIMINARY DATA SHEET
256MB Unbuffered DDR SDRAM DIMM
EBD25EC8AKFA-5
(32M words
×
72 bits, 1 Rank)
Description
The EBD25EC8AKFA is 32M words
×
72 bits, 1 rank
Double Data Rate (DDR) SDRAM unbuffered module,
mounting 9 pieces of 256M bits DDR SDRAM sealed in
TSOP package.
Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
•
184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
•
2.5 V power supply
•
Data rate: 400Mbps (max.)
•
2.5 V (SSTL_2 compatible) I/O
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs and outputs are synchronized with DQS
•
4 internal banks for concurrent operation
(Component)
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
Programmable burst length: 2, 4, 8
•
Programmable /CAS latency (CL): 3
•
Programmable output driver strength: normal/weak
•
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0354E30 (Ver. 3.0)
Date Published June 2003 (K) Japan
URL: http://www.elpida.com
Elpida
Memory , Inc. 2003
EBD25EC8AKFA-5
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/RAS
/CAS
/WE
/CS0
CKE0
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS8
DM0 to DM8/DQS9 to DQS17
SCL
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
VDDID
NC
Function
Address input
Row address
Column address
Data input/output
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
VDD identification flag
No connection
A0 to A12
A0 to A9
Bank select address
Preliminary Data Sheet E0354E30 (Ver. 3.0)
4
EBD25EC8AKFA-5
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
Bit5 Bit4
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
Bit3
0
1
0
1
1
0
1
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
Bit2
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
Bit1 Bit0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
Hex value
80H
08H
07H
0DH
0AH
01H
48H
00H
04H
50H
70H
02H
82H
08H
08H
01H
0EH
04H
1CH
01H
02H
20H
C0H
60H
70H
75H
75H
3CH
48H
28H
3CH
48H
28H
40H
Comments
128 bytes
256 bytes
DDR SDRAM
13
10
1
72 bits
0
SSTL2
5.0ns
*1
0.7ns
*1
ECC
7.8µs
×
8
×
8
1 CLK
2,4,8
4
2, 2.5, 3
0
1
Differential
Clock
VDD ± 0.2V
6.0ns
*1
0.7ns
*1
0.75ns
*1
0.75ns
*1
15ns
18ns
10ns
15ns
18ns
40ns
256M bytes
Voltage interface level of this assembly 0
DDR SDRAM cycle time, CL = 3
SDRAM access from clock (tAC)
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at CL = 2.5
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
Maximum data access time (tAC) from
0
clock at CL = 2.5
Minimum clock cycle time at CL = 2
0
Maximum data access time (tAC) from
0
clock at CL = 2
Minimum row precharge time (tRP)
0
-5B
-5C
0
0
0
0
0
0
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
-5B
-5C
Minimum active to precharge time
(tRAS)
Module rank density
28
29
30
31
Preliminary Data Sheet E0354E30 (Ver. 3.0)
5
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