LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-
3.3V, 2.5V LVPECL FANOUT BUFFER
ICS853S12I
G
ENERAL
D
ESCRIPTION
The ICS853S12I is a low skew, 1-to-12 Differential-
to-3.3V, 2.5V LVPECL Fanout Buffer and a member
HiPerClockS™
of the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The PCLK, nPCLK pair
accepts LVPECL, CML, and SSTL differential input
levels. The high gain differential amplifier accepts peak-to-peak
input voltages as small as 150mV, as long as the common mode
voltage is within the specified minimum and maximum range.
F
EATURES
•
Twelve differential 3.3V, 2.5V LVPECL outputs
•
PCLK, nPCLK input pair
•
PCLK, nPCLK pair can accept the following differential
input levels: LVPECL, CML, SSTL
•
Maximum output frequency: 1.5GHz
•
Translates any single-ended input signal to 2.5V or 3.3V
LVPECL levels with a resistor bias on nPCLK input
•
Additive phase jitter, RMS: 0.06ps (typical)
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 680ps (maximum)
•
Full 3.3V or 2.5V operating supply modes
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
IC
S
Guaranteed output and part-to-part skew characteristics make
the ICS853S12I ideal for those clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
PCLK
Pulldown
nPCLK
Pullup/Pulldown
P
IN
A
SSIGNMENT
32 31 30 29 28 27 26 25
Q11
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
CC
nQ1
nQ2
nQ3
V
CC
Q1
Q2
Q3
nQ10
nQ9
nQ8
Q10
V
CC
V
CC
Q9
Q8
24
23
nQ7
Q7
nQ6
Q6
nQ5
Q5
nQ4
Q4
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
Q7
nQ7
Q6
nQ6
nQ11
V
EE
PCLK
nPCLK
V
EE
Q0
nQ0
ICS853S12I
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
22
21
20
19
18
17
IDT
™
/ ICS
™
LVPECL FANOUT BUFFER
1
ICS853S12AKI REV. A MAY 21, 2008
ICS853S12I
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 6
4
5
7, 8
9, 10
11, 16, 25, 30
12 , 1 3
14, 15
17, 18
Name
Q11, nQ11
V
EE
PCLK
nPCLK
Q0, nQ0
Q1, nQ1
V
CC
Q2, nQ2
Q3, nQ3
Q4, nQ4
Type
Output
Power
Input
Input
Output
Output
Power
Output
Output
Output
Description
Differential output pair. LVPECL interface levels.
Negative supply pins.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input.
Pulldown
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Positive supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
19, 20
Q5, nQ5
Output
Differential output pair. LVPECL interface levels..
Differential output pair. LVPECL interface levels.
21, 22
Q6, nQ6
Output
23, 24
Q7, nQ7
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
28, 29
Q9, nQ9
Output
26, 27
Q8, nQ8
Output
Differential output pair. LVPECL interface levels.
Q10, nQ10
Output
Differential output pair. LVPECL interface levels.
31, 32
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q11
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ11
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information "Wiring the Differential Input to Accept Single Ended Levels".
IDT
™
/ ICS
™
LVPECL FANOUT BUFFER
2
ICS853S12AKI REV. A MAY 21, 2008
ICS853S12I
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any con-
ditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may
affect product reliability.
Package Thermal Impedance,
θ
JA
For 32 Lead VFQFN
42.7°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
137
Units
V
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
130
Units
V
mA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%
OR
2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
I
IH
Input High Current
PCLK
nPCLK
PCLK
I
IL
V
PP
V
CMR
V
OH
V
OL
Input Low Current
nPCLK
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
-10
-150
0.3
V
EE
+ 1.5
V
CC
- 1.3
V
CC
- 2.0
1.0
V
CC
V
CC
- 0.8
V
CC
- 1.6
1.0
Minimum
Typical
Maximum
150
10
Units
µA
µA
µA
µA
V
V
V
V
V
V
SWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
- 2V.
IDT
™
/ ICS
™
LVPECL FANOUT BUFFER
3
ICS853S12AKI REV. A MAY 21, 2008
ICS853S12I
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%
OR
, V
CC
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
80
300
622MHz, Integration Range:
12kHz – 20MHz
0.06
50
250
300
53
Test Conditions
Minimum
Typical
Maximum
1.5
680
Units
GHz
ps
ps
ps
ps
ps
%
t
jit
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle
47
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
LVPECL FANOUT BUFFER
4
ICS853S12AKI REV. A MAY 21, 2008
ICS853S12I
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
622MHz (12kHz to 20MHz) = 0.06ps typical
SSB P
HASE
N
OISE
dBc/H
Z
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT
™
/ ICS
™
LVPECL FANOUT BUFFER
5
ICS853S12AKI REV. A MAY 21, 2008
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