Data Sheet No. PD60234 revB
IR22771S/IR21771S(PbF)
Phase Current Sensor IC for AC motor control
Features
•
Floating channel up to 600V for IR21771 and 1200V for
IR22771
Product Summary
V
OFFSET
(max)
V
in
range
Bootstrap supply range
Floating channel quiescent
current (max)
Sensing latency (max)
Throughput
Over Current threshold (max)
IR22771
IR21771
1200 V
600V
±250mV
8-20 V
2.2 mA
7.5 µsec
(@20kHz)
40ksample/sec
(@20kHz)
±470 mV
•
•
•
•
•
•
Synchronous sampling measurement system
High PWM noise (ripple) rejection capability
Digital PWM output
Fast Over Current detection
Suitable for bootstrap power supplies
Low sensing latency (<7.5
µsec
@20kHz)
Description
IR21771/IR22771 is a high voltage, high speed, single phase
current sensor interface for AC motor drive applications. The
current is sensed by an external shunt resistor. The IC converts the
analog voltage into a time interval through a precise circuit that also
performs a very good ripple rejection showing small group delay.
The time interval is level shifted and given to the output. The max
throughput is 40 ksample/sec suitable for up to 20 kHz
asymmetrical PWM modulation and max delay is <7.5
µsec
(@20kHz). Also a fast over current signal is provided for IGBT
protection.
Package
Typical Connection
(Please refer to
Lead Assignments
for correct pin
configuration. This
diagram shows
electrical
connections only)
1
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IR22771S/IR21771S(PbF)
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to V
SS
; all currents are defined positive into any lead. The Thermal Resistance and Power
Dissipation ratings are measured under board mounted and still air conditions.
Symbol
V
B
V
S
V
in+
/ V
in-
G0 / G1
V
CC
Sync
PO
OC
dVS/dt
P
D
R
thJA
T
J
T
S
T
L
Definition
High Side Floating Supply Voltage
High Side Floating Ground Voltage
High-Side Inputs Voltages
High-Side Range Selectors
Low-Side Fixed Supply Voltage
Low-Side Input Synchronization Signal
PWM Output
Over Current Output Voltage
Allowable Offset Voltage Slew Rate
Maximum Power Dissipation
Thermal Resistance, Junction to Ambient
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
IR22771
IR21771
Min.
- 0.3
- 0.3
V
B
- 25
V
B
- 5
V
B
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
Max.
1225
625
V
B
+ 0.3
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
50
250
90
125
150
300
Units
V
V
V
V
V
V
V
V
V
V/ns
mW
ºC/W
ºC
ºC
ºC
-40
-55
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to
V
SS
. The
V
S
offset rating is tested with all supplies biased at 15V differential.
Symbol
V
BS
V
S
V
in+
/ V
in-
G0 / G1
V
CC
Sync
f
sync
PO
OC
T
A
Definition
High Side Floating Supply Voltage (V
B
- V
S
)
High Side Floating Ground Voltage
High-Side Inputs Voltages
High-Side Range Selectors
Low Side Logic Fixed Supply Voltage
Low-Side Input Synchronization Signal
Sync Input Frequency
PWM Output
Over Current Output Voltage
Ambient Temperature
IR22771
IR21771
Min.
V
S
+ 8.0
-5
-5
V
S
- 5.0
Note 1
8
V
SS
4
-0.3
-0.3
-40
Max.
V
S
+ 20
1200
600
V
S
+ 5.0
Note1
20
V
CC
20
Note 2
Note 2
125
Units
V
V
V
V
V
V
kHz
V
V
ºC
Note 1:
Shorted to V
S
or V
B
Note 2:
Pull-Up Resistor to V
CC
2
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IR22771S/IR21771S(PbF)
Static Electrical Characteristics
V
CC
, V
BS
= 15V unless otherwise specified. Temp=27°C; V
in
=V
in+
- V
in
.
Pin: V
CC
, V
SS
, V
B
, V
S
Symbol
I
QBS
I
QCC
Definition
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Offset supply leakage
current
IR22771
IR21771
Min
Typ
1
Max
2.2
6
50
50
Units
mA
mA
µA
µA
Test
Conditions
f
sync
= 10kHz,
20kHz
f
sync
= 10kHz,
20kHz
V
B
= V
S
=
1200V
V
B
= V
S
= 600V
I
LK
Pin: V
in+
, V
in-
, Sync, G0, G1, OC
Symbol
V
inmax
V
inmin
V
IH
V
IL
V
hy
I
vinp
I
pu
|V
octh
|
R
Sync
R
onOC
Definition
Maximum input voltage before saturation
Minimum input voltage before saturation
Sync Input High threshold
Sync Input Low threshold
Sync Input Hysteresis
V
in+
input current
G0, G1 pull-up Current
Over Current Activation Threshold
SYNC to V
SS
internal pull-down
Over Current On Resistance
Min
Typ
250
-250
Max
Units
mV
mV
V
V
V
Test
Conditions
2.2
0.8
0.2
-18
-20
300
6
25
-6
-8
470
12
75
See Figure 1
See Figure 1
See Figure 1
f
sync
= 4kHz to
20kHz
G1, G0 = V
B
-
5V
µA
µA
mV
kΩ
Ω
@ I = 2mA
See Figure 3
Schmitt trigger
SYNC
R
sync
V
SS
V
IL
V
hy
V
IH
Figure 2:
Sync input circuit
Figure 1:
Sync input thresholds
3
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IR22771S/IR21771S(PbF)
Pin: PO
Symbol
Definition
Min
Typ
Max
Units
Test
Conditions
R
pull-up
=500
Ω
f
sync
= 4, 20kHz
V
threshold
=2.75V
Ext supply=5V
(See Figure 6)
V
POs
Input offset voltage measured by PWM
output
-50
20
mV
∆V
POs
/
∆Tj
∆V
Pos
G
p
∆G
p
/
∆Tj
CMRR
PO
V
Polin
Input offset voltage temperature drift
∆offset
between samples on channel1
and channel2 measured at PO (See
Note1)
PWM Output Gain
PWM Output Gain Temperature Drift
PO Output common mode (V
S
) rejection
PO Linearity
-10
-38
TBD
10
-40.5
TBD
0.2
0.07
TBD
0.8
1.6
0.2
25
75
0.2
-42.5
µV/°C
mV
%/V
%/(V
*
ºC)
m%/V
%
%/ºC
V
%/V
Ω
V
S
-V
SS
= 0,
600V
f
sync
= 10kHz
f
sync
= 10kHz
f
sync
= 10kHz
OC active (See
Figure 4)
V
CC
=V
BS
=
8,20V
@ I = 2mA
See Figure 3
f
sync
= 10kHz
See Figure 6
V
in
=±250mV
∆
V
lin
/
∆Tj
PO Linearity Temperature Drift
V
thPO
PO threshold for OC reset
PSRR PO PSRR for PO Output
R
onPO
PO On Resistance
Note1:
Refer to PO output description for channels definition
PO
or
OC
R
ON
V
SS
Internal signal
Figure 3:
PO and OC open collector circuit
4
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IR22771S/IR21771S(PbF)
AC Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V unless otherwise specified. Temp=27°C.
Symbol
f
sync
f
out
BW
GD
D
min
D
max
t
dOCon
T
OCoff
MD
SR
Definition
PWM frequency
Throughput
Bandwidth (@ -3 dB)
Group Delay (input filter)
Minimum Duty Cycle (Note 1)
Maximum Duty Cycle (Note 1)
De-bounce time of OC
Time to reset OC forcing PO
Measure Delay
Step response (max time to reach
steady state)
Min
4
Typ
Max
20
Units
kHz
ksample/sec
kHz
µs
%
%
Test
Conditions
2
⋅
fsync
fsync
1
4
⋅
fsync
10
30
2.7
3.5
4.7
0.5
0.30
2
⋅
fsync
1 .3
fsync
V
in
=+V
inmax
V
in
=-V
inmin
See Figure 4
See Figure 4
µs
µs
µs
µs
0.51
fsync
See Figure 5
Note 1:
negative logic, see fig. 4 on page 7
Note 2:
Cload < 5 nF avoids overshoot
Figure 4:
OC timing diagram
5
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