BelaSigna R262
Wideband Voice Capture
and Noise Reduction
Solution
Introduction
BelaSigna
®
R262 is a complete system−on−chip (SoC) solution that
provides wideband advanced noise reduction in voice capture
applications such as mobile phones, VoIP applications including
webcams and tablet computers, two−way radios and other applications
that can benefit from improved voice clarity.
Featuring a novel approach to removing mechanical, stationary and
non−stationary noise, the chip preserves voice naturalness for greater
voice clarity and speech intelligibility even when the talker is further
away or not optimally aligned with the microphones, providing
unmatched freedom of movement for end−users. Designed to be
compatible with a wide range of codecs, baseband chips and
microphones without the need for calibration, BelaSigna R262 is easy
to integrate, improving manufacturers’ time to market.
Additional features include the ability to provide two
simultaneously processed outputs and to configure them depending on
the needs of a manufacturer’s device. The chip includes a highly
optimized DSP−based application controller with industry−leading
energy efficiency and is packaged in a highly compact 5.3 mm
2
WLCSPs to fit into even the most sized−constrained architectures
while allowing the use of common industry printed circuit board
design technologies.
Key Features and Benefits
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WLCSP−30
W SUFFIX
CASE 567CT
WLCSP−26
W SUFFIX
CASE 567CY
MARKING DIAGRAMS
1
BR262
W30
ALYW
BR262
W30
W26
A
L
YW
1
BR262
W26
ALYW
•
Drop−in Solution that Works without Special Tuning
•
Consistently Captures Voice Regardless of Acoustic Environment or
•
•
•
•
•
•
the Orientation of the Handheld Device While in Use
360° Voice Pick−up Adjustable From 5 cm to 5 m
No Constraints on Industrial Design or Microphone Model
Simultaneous Dual−configurable Outputs
De−reverberation
Low Power Consumption (17 mA active and 40
mA
stand−by)
Miniature Size Allows Easy Integration into Existing Industrial
Designs
Mobile Phones
Notebook and Tablet Computers
Two−Way Radios and PTT Devices
VoIP Applications
Any Device that would Benefit from Improved Voice Pick−up
= BelaSigna R262
= 30−ball version
= 26−ball version
= Assembly Location
= Wafer Lot
= Date Code Year & Week
= Pb−Free Package
= A1 Corner Indicator
ORIENTATION
•
•
•
•
•
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 22 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
November, 2012
−
Rev. 2
1
ÈÈ
ÈÈ
Typical Applications
1
(Top View)
Publication Order Number:
BR262/D
BR262
W30
ALYW
BelaSigna R262
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply (Applies on VBAT, VBATRCVR and VDDO for “Max” and for
VSSA, VSSRCVR and VSSD for “Min”) (Note 1)
Digital input pin voltage
Operating temperature range
Storage temperature range
Min
−0.3
VSSD
−
0.3 V
−40
−40
Max
4.0
VDDO + 0.3 V
85
85
Unit
V
V
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Time limit at maximum voltage must be less than 100 ms.
NOTE: Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
This device series incorporates ESD protection and is tested by the following methods:
−
ESD Human Body Model (HBM) tested per AEC−Q100−002 (EIA/JESD22−A114)
−
ESD Machine Model (MM) tested per AEC−Q100−003 (EIA/JESD22−A115)
This device series incorporates latch−up immunity and is tested in accordance with JESD78.
Electrical Performance Specifications
Table 2. ELECTRICAL CHARACTERISTICS
(The typical parameters in Table 2 were measured at 20°C with a clean
3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified
for all process corners but not tested on every part.)
Parameter
OVERALL
Supply voltage
Maximum rise time
Average current consumption
VBAT
Between 0 V and 1.8 V
Active mode, VBAT = 3.3 V,
EXT_CLK = 2.048 MHz
Bypass mode, VBAT = 3.3 V,
EXT_CLK = 2.048 MHz
Bypass mode, VBAT = 3.3 V,
Internal clock
Sleep mode, VBAT = 3.3 V
Peak active current
VREG (1
mF
External Capacitor)
Output voltage
PSRR
Load regulation
Load current
Line regulation
−1
VREG
Without load, or with micro-
phone attached (0 to 200
mA)
@ 1 kHz
@ 2 mA
0.95
40
5
20
2
5
1.00
1.05
V
dB
mV/mA
mA
mV/V
l
VBAT = 3.63 V
16.0
16.0
2.7
39
16.5
16.5
2.8
40
19
21
1.65
3.3
3.63
10
17.0
17.0
2.9
V
ms
mA
mA
mA
mA
mA
Symbol
Test Conditions / Notes
Min
Typ
Max
Unit
Screened
VDDA (1
mF
External Capacitor on VDDA + 100 nF External Capacitor on CAP0/CAP1)
Output voltage
PSRR
Load regulation
Load current
Line regulation
VDDD (1
mF
External Capacitor)
Output voltage
VDDD
1.62
1.70
1.98
V
l
VDDA
Unloaded with VREG = 1 V
@ 1 kHz
@ 1 mA
1.8
45
100
140
1
2
2.0
2.1
V
dB
mV/mA
mA
mV/V
l
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BelaSigna R262
Table 2. ELECTRICAL CHARACTERISTICS
(continued) (The typical parameters in Table 2 were measured at 20°C with a clean
3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified
for all process corners but not tested on every part.)
Parameter
VMIC
Output voltage
VMIC = VREG
VMIC = VDDA
Load Regulation
VMIC = VREG
VMIC = VDDA
POWER ON RESET
POR Threshold
POR Release
(VBAT going up)
POR Activation
(VBAT going down)
Boot Time
NRST to DMIC active using
LSAD boot method
NRST to DMIC active using
SPI EEPROM boot method
(Default custom application)
NRST to DMIC active using
I2C EEPROM boot method
(Default custom application)
INPUT STAGE
Sampling frequency
Analog input voltage
Fs
Vin
Vin
Preamplifier gain tolerance
Input impedance
Rin
Defined by ROM−based
application. (Note 2)
No preamp gain on AI1
and AI3
24 dB preamp gain by default
on MIC0 and MIC2
1 kHz
0 dB preamplifier gain
All other gain settings
Input offset voltage
0 dB preamp gain
All other gains
Channel cross coupling
Analog Filter cut−off frequency
Any 2 channels
LPF enabled (default)
LPF disabled
Analog Filter passband flatness
Analog filter stopband
attenuation
Digital Filter cut−off frequency
Digital Filter cut−off stopband
attenuation
Total Harmonic Distortion +
Noise (Peak value)
Dynamic Range
Equivalent Input Noise
THDN
DR
EIN
24 dB preamplifier gain
VBAT = 3.3 V
24 dB preamplifier gain
VBAT = 3.3 V
24 dB preamplifier gain
VBAT = 3.3 V
80
−67
81
−70
82.5
3.7
10
50
−1
60
Fs/2
1
−84
20
510
0
0
−2
250
585
7
3
−60
30
21.333
2
125
2
kHz
Vpp
mVpp
dB
kW
kW
mV
mV
dB
kHz
kHz
dB
dB
kHz
dB
dB
dB
mV
l
1.52
1.52
1.60
1.60
16.3
90
1.71
1.65
V
V
ms
ms
l
l
0.95
1.8
1.00
2.0
25
100
1.05
2.1
40
150
V
V
mV/mA
mV/mA
l
l
Symbol
Test Conditions / Notes
Min
Typ
Max
Unit
Screened
135
ms
2. Processed bandwidth limited to 8 kHz.
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BelaSigna R262
Table 2. ELECTRICAL CHARACTERISTICS
(The typical parameters in Table 2 were measured at 20°C with a clean
3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified
for all process corners but not tested on every part.)
Parameter
DIGITAL MICROPHONE OUTPUT
DMIC input clock frequency
With preset 0 selected on
CLOCK_SEL (Note 3)
With preset 3 selected on
CLOCK_SEL (Note 3)
With preset 4 selected on
CLOCK_SEL (Note 3)
With preset 5 selected on
CLOCK_SEL (Note 3)
Clock duty cycle
Input clock jitter
Clock to output transition time
ANALOG OUTPUT STAGE
Signal Range
Vout
One single ended DAC used
Two DACs used as one
differential output
Attenuator gain tolerance
Output impedance
Rout
@ 12 dB output attenuation
@ 0 dB output attenuation
Channel cross coupling
Analog Filter cut−off frequency
@ 1 kHz
LPF Enabled (default)
LPF Disabled
Analog Filter passband flatness
Analog filter stopband
attenuation
Digital Filter cut−off frequency
Digital Filter cut−off stopband
attenuation
Total Harmonic Distortion +
Noise (Peak value)
Dynamic Range
Noise Floor
DIRECT DIGITAL OUTPUT (available only through custom configuration)
Supply voltage
Signal Range
VBATRCVR
Vout
Differential Output @ 1 kHz
Single ended Output @ 1 kHz
Output Impedance
Maximum Current
Total Harmonic Distortion +
Noise (Peak value)
THDN
64
70
Rout
Load between
1 mA and 30 mA @ 0°C
1.8
0
0
2.5
3.3
3.63
2*VBAT
RCVR
VBAT
RCVR
10
25
V
Vpp
Vpp
W
mA
dB
l
THDN
DR
80
63
78
65
80
70
100
> 60 kHz
13.0
25
−1
90
Fs/2
0
0
−2
2
4
2
19
3
−50
13.5
26
1
Vpp
Vpp
dB
kW
kW
dB
kHz
kHz
dB
dB
kHz
dB
dB
dB
mV
l
l
l
l
DMIC_OUT
Any clock configuration
Maximum allowed jitter on the
DMIC_CLK
10
20
40
2.048
2.4
2.8
3.072
50
60
10
50
MHz
MHz
MHz
MHz
%
ns
ns
Symbol
Test Conditions / Notes
Min
Typ
Max
Unit
Screened
3. Many other clock frequencies are available through custom configuration of the internal PLL and clocking subsystem. See later in this
document and in the BelaSigna R262 Communications and Configuration Guide for more information on custom mode usage.
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BelaSigna R262
Table 2. ELECTRICAL CHARACTERISTICS
(continued) (The typical parameters in Table 2 were measured at 20°C with a clean
3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified
for all process corners but not tested on every part.)
Parameter
Symbol
Test Conditions / Notes
Min
Typ
Max
Unit
Screened
DIRECT DIGITAL OUTPUT (available only through custom configuration)
Dynamic Range
Noise Floor
LOW−SPEED A/D
Input voltage
Sampling frequency
Input impedance
Offset error
Gain error
INL
DNL
DIGITAL PADS (VDDO = 1.8 V)
Voltage level for Low input
Voltage level for High input
Pull−up resistance
Pull−down resistance
Rise and Fall Time
DIGITAL PADS (VDDO = 3.3 V)
Voltage level for Low input
Voltage level for High input
Pull−up resistance
Pull−down resistance
Rise and Fall Time
DIGITAL PADS (Common parameters)
Drive Strength
ESD Immunity
HBM
MM
Latch−up Immunity
CLOCKING CIRCUITRY
External clock frequency
Internal clock frequency
EXT_CLK
INT_CLK
With preset 6 selected on
CLOCK_SEL (Note 3)
With preset 7 selected on
CLOCK_SEL (Note 3)
Bypass Mode
With preset 7 selected on
CLOCK_SEL (Note 3)
Active Mode
Reference clock duty cycle
External Input clock jitter
I
2
C INTERFACE
Maximum speed
400
kbps
Maximum allowed jitter on
EXT_CLK
40
26
5.2
MHz
MHz
Human Body Model
Machine Model
25°C, V < GNDO, V > VDDO
2
200
150
12
mA
kV
V
mA
20 pF load
VIL
VIH
−0.3
1.8
34
29
1.0
46
56
1.5
0.8
3.6
74
86
2.0
V
V
kW
kW
ns
l
l
l
l
20 pF load
VIL
VIH
−0.3
1.30
63
87
2
114
153
3
0.4
1.98
162
205
5
V
V
kW
kW
ns
INL
DNL
Rin
Input at VREG
Input to VSSA or 2*VREG
Vin
For each LSAD channel
0
1.6
1
−10
−10
−4
−2
10
10
4
2
MCLK/28
2*VREG
4.8
V
kHz
MW
LSB
LSB
LSB
LSB
DR
80
86
50
75
dB
mV
l
l
48.2
MHz
50
60
10
%
ns
3. Many other clock frequencies are available through custom configuration of the internal PLL and clocking subsystem. See later in this
document and in the BelaSigna R262 Communications and Configuration Guide for more information on custom mode usage.
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