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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4515
4-to-16 line decoder/demultiplexer
with input latches; inverting
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
FEATURES
•
Inverting outputs
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4515 are high-speed Si-gate CMOS
devices and are pin compatible with “4515” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT4515
The 74HC/HCT4515 are 4-to-16 line
decoders/demultiplexers having four binary weighted
address inputs (A
0
to A
3
) with latches, a latch enable input
(LE), and an active LOW enable input (E). The 16 inverting
outputs (Q
0
to Q
15
) are mutually exclusive active LOW.
When LE is HIGH, the selected output is determined by the
data on A
n
. When LE goes LOW, the last data present at
A
n
are stored in the latches and the outputs remain stable.
When E is LOW, the selected output, determined by the
contents of the latch, is LOW. When E is HIGH, all outputs
are HIGH. The enable input (E) does not affect the state of
the latch.
When the “4515” is used as a demultiplexer, E is the data
input and A
0
to A
3
are the address inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+∑ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay A
n
to Q
n
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
25
3.5
44
HCT
26
3.5
46
ns
pF
pF
UNIT
September 1993
2
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
PIN DESCRIPTION
PIN NO.
1
2, 3, 21, 22
12
23
24
SYMBOL
LE
A
0
to A
3
GND
E
V
CC
74HC/HCT4515
NAME AND FUNCTION
latch enable input (active HIGH)
address inputs
multiplexer outputs (active LOW)
ground (0 V)
enable input (active LOW)
positive supply voltage
11, 9, 10, 8, 7, 6, 5, 4,18, 17, 20, 19, 14, 13, 16, 15 Q
0
to Q
15
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
74HC/HCT4515
APPLICATIONS
•
Digital multiplexing
•
Address decoding
•
Hexadecimal/BCD decoding
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
E
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes
1. LE = HIGH
H = HIGH voltage level
L = LOW voltage level
X = don’t care
A
0
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
A
1
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
2
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
A
3
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Q
0
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
1
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
2
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
3
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
Q
4
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
Q
5
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
Q
6
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
OUTPUTS
Q
7
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
Q
8
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
Q
9
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
Q
10
Q
11
Q
12
Q
13
Q
14
Q
15
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
September 1993
4
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