Revision 3
40MX and 42MX Automotive FPGA Families
Features
High Capacity
•
•
•
•
•
Single-Chip
Applications
ASIC
Alternative
for
Automotive
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
•
•
Ease of Integration
•
•
•
Up to 100% Resource Utilization and 100% Pin Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
Capacity
System Gates
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
Maximum User I/Os
Boundary Scan Test (BST)
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
A40MX02
3,000
–
–
295
–
–
–
147
1
57
–
PL68
PQ100
VQ80
–
A40MX04
6,000
–
–
547
–
–
–
273
1
69
–
PL84
PQ100
VQ80
–
A42MX09
14,000
–
348
336
–
–
348
516
2
104
–
PL84
PQ100,
PQ160
VQ100
TQ176
A42MX16
24,000
–
624
608
–
–
624
928
2
140
–
–
PL208
PQ100
VQ176
A42MX24
36,000
–
954
912
24
–
954
1,410
2
176
Yes
–
PQ160,
PQ208
–
TQ176
A42MX36
54,000
2,560
1,230
1,184
24
10
1,230
1,822
6
202
Yes
–
PQ208,
PQ240
–
–
Note:
While the automotive-grade MX devices are offered in standard speed grade only, the MX family is also offered in commercial,
industrial and military temperature grades with -F, Std, -1, -2 and -3 speed grades. Refer to the
40MX and 42MX Family
FPGAs
datasheet for more details.
May 2012
© 2012 Microsemi Corporation
i
40MX and 42MX Automotive FPGA Families
Ordering Information
A42MX16 _
PQ
G
208
A
Application (Temperature Range)
A = Automotive (–40 to +125°C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
PL = Plastic Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
TQ = Thin Quad Flat Pack (1.4 mm)
VQ = Very Thin Quad Flat Pack (1.0 mm)
Speed Grade
(Blank for Standard)
Part Number
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
=
=
=
=
=
=
3,000 System Gates
6,000 System Gates
14,000 System Gates
24,000 System Gates
36,000 System Gates
54,000 System Gates
Note:
Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based
on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If
testing to ensure guaranteed operation at extended temperatures is required, please contact your local SoC Products Group
Sales office to discuss testing options available.
Plastic Device Resources
User I/Os
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
PL68
57
–
–
–
–
–
PL84
–
69
72
–
–
–
PQ100
57
69
83
–
–
–
PQ160
–
–
101
–
125
–
PQ 208
–
–
–
140
176
176
PQ240
–
–
–
–
–
202
VQ80
57
69
–
–
–
–
VQ100
–
–
83
83
–
–
TQ176
–
–
104
140
150
–
Note:
Package Definitions
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad
Flat Pack
Speed Grade and Temperature Grade Matrix
Application (Temperature Range)
A
Std
✓
Note:
Refer to the
40MX and 42MX Family FPGAs
datasheet for details on commercial-, industrial- and military-grade MX offerings.
Contact your local Microsemi SoC Products Group representative for device availability.
ii
R ev i si o n 3
40MX and 42MX Automotive FPGA Families
Table of Contents
40MX and 42MX Automotive FPGA Families
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Timing Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Sequential Timing Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Temperature and Voltage Derating Factors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47
Package Pin Assignments
PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Revision 3
iii
1 – 40MX and 42MX Automotive FPGA Families
General Description
Microsemi’s automotive-grade MX families provide a high-performance, single-chip solution for
shortening the system design and development cycle, offering a cost-effective alternative to ASICs for in-
cabin telematics and automobile interconnect applications. The 40MX and 42MX devices are excellent
choices for integrating logic that is currently implemented in multiple PALs, CPLDs, and FPGAs.
The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a
0.45µm triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX
devices are live on power-up and have one-fifth the standby power consumption of comparable FPGAs.
MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed
grades.
The automotive-grade 42MX24 and 42MX36 include system-level features such as IEEE Standard
1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device
offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage
elements can efficiently address applications requiring wide datapath manipulation.
MX Architectural Overview
The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All
devices within these families are composed of logic modules, I/O modules, routing resources and clock
networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains
embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as
FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain wide-decode modules.
Logic Modules
The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of
logic functions with efficient use of interconnect routing resources (Figure
1-1).
Figure 1-1 •
40MX Logic Module
The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of
two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity
functions, AND-ORs and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the
array; latches and flip-flops can be constructed from logic modules whenever required in the
application.
Revision 3
1 -1
FPGA/CPLD
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