CY25404
Quad PLL Programmable Clock Generator
with Spread Spectrum
Features
■
■
Four fully-integrated phase-locked loops (PLLs)
Input frequency range
❐
External crystal: 8 to 48 MHz
❐
External reference: 8 to 166 MHz clock
Wide operating output frequency range
❐
3 to 166 MHz
Programmable spread spectrum with center and down
spread option and lexmark and linear modulation profiles
Selectable V
DD
supply voltage options:
❐
2.5 V, 3.0 V, and 3.3 V
Selectable output clock voltages, independent of V
DD
supply:
❐
1.8 V, 2.5 V, 3.0 V, and 3.3 V
Frequency select feature with option to select eight different
frequencies over nine clock outputs
Output enable, and SS ON/OFF controls
Low jitter, high accuracy outputs
Ability to synthesize nonstandard frequencies with
Fractional-N capability
Up to nine clock outputs with programmable drive strength
Glitch-free outputs while frequency switching
20-pin TSSOP package
Commercial and Industrial temperature ranges
■
One-time programmability
For programming support, contact
Cypress technical support
or send an email to
clocks@cypress.com
Benefits
■
■
■
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
Application specific programmable electromagnetic
interference (EMI) reduction using spread spectrum for
clocks
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system
designs
Suitability for PC, consumer, portable, and networking
applications
Capable of zero parts per million (PPM) frequency synthesis
error
Uninterrupted system operation during clock frequency
switch
Application compatibility in standard and low-power systems
■
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For a complete list of related documentation, click
here.
Block Diagram
XIN/
EXCLKIN
XOUT
OSC
PLL1
Crossbar
Switch
Output
Dividers
and
Bank
2
Bank
1
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Control
Bank
3
FS 0
FS 1
FS 2
MUX
and
Control
Logic
PLL2
Drive
Strength
CLK8
CLK9
PLL3
(SS)
PLL4
(SS)
SSON
OE
Cypress Semiconductor Corporation
Document #: 001-43258 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 19, 2017
CY25404
Contents
General Description ......................................................... 4
Four Configurable PLLs .............................................. 4
Input Reference Clocks ............................................... 4
V
DD
Power Supply Options ......................................... 4
Output Bank Settings .................................................. 4
Output Source Selection ............................................. 4
Spread Spectrum Control ............................................ 4
Frequency Select ........................................................ 4
Glitch-Free Frequency Switch ..................................... 4
Output Enable Mode ................................................... 4
Output Drive Strength .................................................. 4
Generic Configuration and Custom Frequency ........... 4
Absolute Maximum Conditions....................................... 5
Recommended Operating Conditions ............................ 5
DC Electrical Specifications ............................................ 6
Recommended Crystal Specification
for SMD Package .............................................................. 7
Recommended Crystal Specification
for Thru-Hole Package ..................................................... 7
AC Electrical Specifications ............................................ 7
Test and Measurement Setup .......................................... 8
Voltage and Timing Definitions ....................................... 8
Ordering Information ........................................................ 9
Possible Configurations ............................................... 9
Ordering Code Definitions ........................................... 9
Package Drawing and Dimensions ............................... 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Document #: 001-43258 Rev. *G
Page 2 of 13
CY25404
Figure 1. Pin Diagram - CY25404 20 LD TSSOP
VDD
XOUT
XIN/EXCLKIN
VSS
1
2
3
4
CY25404
20
CLK9
19
VSS
18
CLK8
17
VDD_CLK_B3
16
CLK7/SSON
15
VDD_CLK_B2
14
CLK6
13
VSS
12
CLK5
11
CLK4/FS2
CLK1
5
VDD_CLK_B1
6
CLK2
VSS
CLK3/FS0
7
8
9
OE/FS1
10
Table 1. Pin Definition - CY25404 (V
DD
= 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number
1
2
3
4
5
6
7
8
9
V
DD
XOUT
XIN/EXCLKIN
V
SS
CLK1
V
DD_CLK_B1
CLK2
V
SS
CLK3/FS0
Name
Power
Output
Input
Power
Output
Power
Output
Power
Output/Input
IO
Power supply: 2.5 V/3.0 V/3.3 V
Crystal output
Crystal input or 1.8 V external clock input
Power supply ground
Programmable clock output with spread spectrum. Output voltage depends on
V
DD_CLK_B1
voltage
Power supply for Bank1, (CLK1, CLK2, CLK3) outputs: 1.8 V/2.5 V/3.0 V/3.3 V
Programmable clock output with spread spectrum. Output voltage depends on
V
DD_CLK_B1
voltage
Power supply ground
Multifunction programmable pin: Programmable clock output with no spread
spectrum or frequency select input pin. Output voltage of CLK3 depends on
V
DD_CLK_B1
voltage
Multifunction programmable pin: High-true output enable or frequency select pin
Multifunction programmable pin: Programmable clock output with no spread
spectrum or frequency select input pin. Output voltage of CLK4 depends on
V
DD_CLK_B2
voltage
Programmable clock output with no spread spectrum. Output voltage depends on
V
DD_CLK_B2
voltage
Power supply ground
Programmable clock output with spread spectrum. Output voltage depends on
V
DD_CLK_B2
voltage
Power supply for Bank2, (CLK4, CLK5, CLK6) outputs: 1.8 V/2.5 V/3.0 V/3.3 V
Multifunction programmable pin. Programmable clock output with spread spectrum
or spread spectrum On/OFF control input pin. Output voltage of CLK7 depends on
V
DD_CLK_B3
voltage
Power supply for Bank3, (CLK7, CLK8, CLK9) outputs: 1.8 V/2.5 V/3.0 V/3.3 V
Programmable clock output with spread spectrum. Output voltage depends on
V
DD_CLK_B3
voltage
Power supply ground
Programmable clock output with spread spectrum. Output voltage depends on
V
DD_CLK_B3
voltage
Page 3 of 13
Description
10
11
OE/FS1
CLK4/FS2
Input
Output/Input
12
13
14
15
16
CLK5
V
SS
CLK6
V
DD_CLK_B2
CLK7/SSON
Output
Power
Output
Power
Output/Input
17
18
19
20
V
DD_CLK_B3
CLK8
V
SS
CLK9
Power
Output
Power
Output
Document #: 001-43258 Rev. *G
CY25404
General Description
Four Configurable PLLs
The CY25404 has four programmable PLLs that can be used to
generate output frequencies ranging from 3 to 166 MHz. The
advantage of having four PLLs is that a single device generates
up to four independent frequencies from a single crystal.
output dividers. This feature enables uninterrupted system
operation while clock frequency is being switched.
Output Enable Mode
There is a multifunction programmable pin 10, OE/FS1 that can
be programmed to operate as output enable (OE) mode. OE is
a high-true input and individual clock outputs can be
programmed to be sensitive to this OE pin. If activated it shuts
off the output drivers, resulting in minimum power consumption
for the device.
Input Reference Clocks
The input to the CY25404 can be either a crystal or a clock
signal. The input frequency range for crystals is 8 MHz to 48
MHz, while that for clock signals is 8 MHz to 166 MHz. The
required voltage level for the input reference clock (EXCLKIN) is
shown in the DC and AC Electrical Specification tables.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values.
Table 2
shows the typical rise
and fall times for different drive strength settings.
Table 2. Output Drive Strength
Output Drive Strength
Low
Mid Low
Mid High
High
Rise/Fall Time (ns)
(Typical Value)
6.8
3.4
2.0
1.0
V
DD
Power Supply Options
This device has programmable power supply option and it can
be programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V.
Output Bank Settings
There are nine clock outputs grouped in three output driver
banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1,
CLK2, CLK3), (CLK4, CLK5, CLK6), and (CLK7, CLK8, CLK9)
respectively. Separate power supplies are used for each of these
banks and they can be any of 1.8 V, 2.5 V, 3.0 V, or 3.3 V. These
voltages are independent of V
DD
power supply used, giving user
multiple choice of output clock voltage levels.
Output Source Selection
These devices have programmable input sources for each of its
nine clock outputs (CLK1–9). There are five available clock
sources for these outputs. These clock sources are:
XIN/EXCLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock source
selection is done using four out of five crossbar switch. Thus, any
one of these five available clock sources can be arbitrarily
selected for the clock outputs. This gives user a flexibility to have
up to four independent clock outputs.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
device, CY25404 can be custom programmed to any desired
frequencies and listed features. For customer specific
programming, contact your local Cypress field application
engineer (FAE) or sales representative.
Output Driver Supply and Multi-Function Input
Restriction
There are three programmable Output/Input function pins for
CLK3/FS0, CLK4/FS2, and CLK7/SSON. These are configu-
rable as clock output or select input or spread spectrum ON/OFF
control input pin.
■
Spread Spectrum Control
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK7/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
When configured as Output, the driver supply voltage is defined
by V
DD_CLK_Bx
and can be individually used with 1.8 V, 2.5 V,
3.0 V, or 3.3 V power supply apart from the V
DD
supply.
When configured as Input, the input threshold level is defined
by V
DD
supply while the protection diode is connected to the
respective V
DD_CLK_Bx
power supply. Therefore, if V
DD_CLK_Bx
is less than V
DD
– 0.5 V, a large leakage current would flow
from the input pin to the V
DD_CLK_Bx
supply. The device does
not permit this condition; it is required that the power supply for
the bank (V
DD_CLK_Bx
) is more than V
DD
– 0.5 V.
■
Frequency Select
There are three multifunction frequency select pins (FS0, FS1
and FS2) that provide an option to select eight different sets of
frequencies among each of the four PLLs. Each output has
programmable output divider options.
Glitch-Free Frequency Switch
When the frequency select pin (FS) is used to switch frequency,
the outputs are glitch-free provided frequency is switched using
Example:
If V
DD_CLK_B2
= 1.8 V, CLK4/FS2 is configured as
FS2, and V
DD
= 3.3 V, there will be a leakage current from FS2
high to V
DD_CLK_B2
. The multi-function pin should only be used
as clock output if the V
DD_CLK_Bx
is less than V
DD
– 0.5 V. In
other words, when these multi-function programmable pins are
configured as input, the power supply for the bank (V
DD_CLK_Bx
)
should be more than V
DD
– 0.5 V.
Document #: 001-43258 Rev. *G
Page 4 of 13
CY25404
Absolute Maximum Conditions
Parameter
V
DD
V
DD_CLK_BX
V
IN
T
S
ESD
HBM
UL-94
MSL
Supply voltage
Output bank supply voltage
Input voltage
Temperature, storage
ESD protection (human body model)
Flammability rating
Moisture sensitivity level
Relative to V
SS
Non functional
JEDEC EIA/JESD22-A114-E
V-0 at 1/8 in.
–
Description
Condition
–
–
Min
–0.5
–0.5
–0.5
–65
2000
–
3
10
Max
4.5
4.5
V
DD
+0.5
+150
Unit
V
V
V
°C
volts
ppm
Recommended Operating Conditions
Parameter
V
DD
V
DD_CLK_BX
T
AC
T
AI
C
LOAD
t
PU
V
DD
operating voltage
Output driver voltage for bank 1, 2 and 3
Commercial ambient temperature
Industrial ambient temperature
Maximum load capacitance
Power-up time for all V
DD
to reach minimum specified voltage (power ramps must
be monotonic)
Description
Min
2.25
1.71
0
–40
–
0.05
Typ
–
–
–
--
–
–
Max
3.60
3.60
+70
+85
15
500
Unit
V
V
°C
°C
pF
ms
Notes
1. Guaranteed by design but not 100% tested.
2. Configuration dependent.
Document #: 001-43258 Rev. *G
Page 5 of 13
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