Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V+ = +1.71V to +5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
Operating Supply Voltage
Power-On-Reset Voltage
Standby Current
(Interface Idle)
Supply Current
(Interface Running)
Input High-Voltage
SDA, SCL, AD0, AD2,
RST,
P0–P7
Input Low-Voltage
SDA, SCL, AD0, AD2,
RST,
P0–P7
Input Leakage Current
SDA, SCL, AD0, AD2,
RST,
P0–P7
Input Capacitance
SDA, SCL, AD0, AD2,
RST,
P0–P7
V+ = +1.71V, I
SINK
= 5mA (QSOP)
V+ = +1.71V, I
SINK
= 5mA (TQFN)
V+ = +2.5V, I
SINK
= 10mA (QSOP)
Output Low Voltage
O8–O15, P0–P7
V
OL
V+ = +2.5V, I
SINK
= 10mA (TQFN)
V+ = +3.3V, I
SINK
= 15mA (QSOP)
V+ = +3.3V, I
SINK
= 15mA (TQFN)
V+ = +5V, I
SINK
= 20mA (QSOP)
V+ = +5V, I
SINK
= 20mA (TQFN)
V+ = +1.71V, I
SOURCE
= 2mA
Output High Voltage
O8–O15
Output Low-Voltage SDA
Output Low-Voltage
INT
Port Input Pullup Resistor
2
SYMBOL
V+
V
POR
I
STB
I+
V
IH
V
IL
I
IH
, I
IL
V+ falling
CONDITIONS
T
A
= -40°C to +125°C
SCL and SDA and other T
A
= -40°C to
digital inputs at V+
+125°C
f
SCL
= 400kHz; other
digital inputs at V+
V+ < 1.8V
V+
≥
1.8V
V+ < 1.8V
V+
≥
1.8V
SDA, SCL, AD0, AD2,
RST,
P0–P7 at V+ or
GND, internal pullup disabled
T
A
= -40°C to
+125°C
MIN
1.71
TYP
MAX
5.50
1.6
UNITS
V
V
µA
µA
V
0.6
23
0.8 x V+
0.7 x V+
1.9
55
0.2 x V+
0.3 x V+
-0.2
10
90
90
110
110
130
130
140
140
V+ - 250 V+ - 30
V+ - 360 V+ - 70
V+ - 260 V+ - 100
V+ - 360 V+ - 120
250
130
25
40
250
55
180
230
210
260
230
280
250
300
+0.2
V
µA
pF
mV
V
OH
V+ = +2.5V, I
SOURCE
= 5mA
V+ = +3.3V, I
SOURCE
= 5mA
V+ = +5V, I
SOURCE
= 10mA
I
SINK
= 6mA
I
SINK
= 5mA
mV
V
OLSDA
V
OLINT
R
PU
mV
mV
kΩ
Maxim Integrated
MAX7325
I
2
C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
PORT AND INTERRUPT
INT
TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
Port Output Data Valid
Port Input Setup Time
Port Input Hold Time
INT
Input Data Valid Time
INT
Reset Delay Time from STOP
INT
Reset Delay Time from
Acknowledge
SYMBOL
t
PPV
t
PSU
t
PH
t
IV
t
IP
t
IR
C
L
≤
100pF
C
L
≤
100pF
C
L
≤
100pF
C
L
≤
100pF
C
L
≤
100pF
C
L
≤
100pF
0
4
4
4
4
CONDITIONS
MIN
TYP
MAX
4
UNITS
µs
µs
µs
µs
µs
µs
TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
Serial-Clock Frequency
Bus Free Time Between a STOP
and a START Condition
Hold Time (Repeated) START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus
Line
RST
Pulse Width
RST
Rising to START Condition
Setup Time
SYMBOL
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD, DAT
t
SU, DAT
t
LOW
t
HIGH
t
R
t
F
t
F,TX
t
SP
C
b
t
W
t
RST
(Notes 3, 4)
(Notes 3, 4)
(Notes 3, 4)
(Note 5)
(Note 3)
500
1
(Note 2)
100
1.3
0.7
20 +
0.1C
b
20 +
0.1C
b
20 +
0.1C
b
50
400
300
300
250
1.3
0.6
0.6
0.6
0.9
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
ns
pF
ns
µs
Note 1:
All parameters are tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 3:
Guaranteed by design.
Note 4:
C
b
= total capacitance of one bus line in pF. I
SINK
≤
6mA. t
R
and t
F
measured between 0.3 x V+ and 0.7 x V+.
Note 5:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Maxim Integrated
3
MAX7325
I
2
C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
STANDBY CURRENT
vs. TEMPERATURE
MAX7325 toc01
SUPPLY CURRENT
vs. TEMPERATURE
f
SCL
= 400kHz
50
SUPPLY CURRENT (µA)
40
30
20
10
V+ = +5.0V
MAX7325 toc02
MAX7325 toc04
2.0
1.8
1.6
STANDBY CURRENT (µA)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V+ = +1.71V
V+ = +2.5V
V+ = +3.3V
V+ = +5.0V
f
SCL
= 0kHz
60
V+ = +3.3V
V+ = +2.5V
V+ = +1.71V
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OUTPUT VOLTAGE LOW
vs. TEMPERATURE
MAX7325 toc03
OUTPUT VOLTAGE HIGH
vs. TEMPERATURE
6
5
OUTPUT VOLTAGE HIGH (V)
4
3
2
1
0
V+ = +3.3V
I
SOURCE
= 5mA
V+ = +2.5V I
SOURCE
= 5mA
V+ = +1.71V I
SOURCE
= 2mA
V+ = +5.0V
I
SOURCE
= 10mA
0.25
V+ = +5.0V
I
SINK
= 20mA
V+ = +3.3V
I
SINK
= 15mA
0.15
OUTPUT VOLTAGE LOW (V)
0.20
0.10
V+ = +2.5V
I
SINK
= 10mA
V+ = +1.71V
I
SINK
= 5mA
0.05
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Pin Description
PIN
QSOP
1
2
3, 21
4–11
12
13–20
22
23
24
—
4
TQFN
22
23
24, 18
1–8
9
10–17
19
20
21
—
NAME
INT
RST
AD2, AD0
P0–P7
GND
O8–O15
SCL
SDA
V+
EP
FUNCTION
Interrupt Output, Active Low.
INT
is an open-drain output.
Reset Input, Active Low. Drive
RST
low to clear the 2-wire interface.
Address Inputs. Select device slave address with AD0 and AD2. Connect AD0 and AD2
to either GND, V+, SCL, or SDA to give four logic combinations (see Tables 2 and 3).
Open-Drain I/O Ports
Ground
Output Ports. O8–O15 are push-pull outputs rated at 20mA.
I
2
C-Compatible Serial-Clock Input
I
2
C-Compatible Serial-Data I/O
Positive Supply Voltage. Bypass V+ to GND with a ceramic capacitor of at least 0.047µF.
Exposed Paddle (TQFN Only). Connect exposed pad to GND.
Maxim Integrated
MAX7325
I
2
C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Detailed Description
MAX7319–MAX7329 Family Comparison
The MAX7324–MAX7327 family consists of four pin-
compatible, 16-port expanders that integrate the func-
tions of the MAX7320 and one of either MAX7319,
MAX7321, MAX7322, or MAX7323.
The MAX7325 is set to two of 32 I
2
C slave addresses
(see Tables 2 and 3) using the address select inputs
AD0 and AD2, and is accessed over an I
2
C serial inter-
face up to 400kHz. The eight outputs and eight I/Os
have different slave addresses. The eight push-pull out-
puts have the 101xxxx addresses and the eight inputs
have addresses with 110xxxx. The
RST
input clears the
serial interface in case of a bus lockup, terminating any
serial transaction to or from the MAX7325.
Configure any port as a logic input by setting the port
output logic-high (logic-high for an open-drain output is
high impedance). When the MAX7325 is read through
the serial interface, the actual logic levels at the ports
are read back.
Functional Overview
The MAX7325 is a general-purpose port expander oper-
ating from a +1.71V to +5.5V supply with eight push-pull
outputs and eight open-drain I/O ports. Each open-drain
output is rated to sink 20mA, and the entire device is
rated to sink 100mA into all ports combined. The outputs
drive loads connected to supplies up to +5.5V.
Table 1. MAX7319–MAX7329 Family Comparison
PART
INPUT
I
2
C
SLAVE
INPUTS INTERRUPT
ADDRESS
MASK
OPEN-
DRAIN
OUTPUTS
PUSH-
PULL
OUTPUTS
CONFIGURATION
16-PORT EXPANDERS
8 input and 8 push-pull output versions:
8 input ports with programmable latching transition
detection interrupt and selectable pullups.
8 push-pull outputs with selectable default logic
levels.
Offers maximum versatility for automatic input
monitoring. An interrupt mask selects which inputs
cause an interrupt on transitions, and transition flags
identify which inputs have changed (even if only
for a transient) since the ports were last read.
8 I/O and 8 push-pull output versions:
8 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
8 push-pull outputs with selectable default logic
levels.
MAX7325
Up to 8
—
Up to 8
8
Open-drain outputs can level shift the logic-high
state to a higher or lower voltage than V+ using
external pullup resistors, but pullups draw current
when output is low. Any open-drain port can be used
as an input by setting the open-drain output to logic-
high. Transition flags identify which open-drain port
inputs have changed (even if only for a transient)
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