NB7V52M
1.8V / 2.5V Differential D
Flip-Flop w/ Reset and CML
Outputs
Multi−Level Inputs w/ Internal Termination
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Description
MARKING
DIAGRAM*
16
1
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
NB7V
52M
ALYWG
G
The NB7V52M is a 10 GHz differential D flip−flop with a
differential asynchronous Reset. The differential D/D, CLK/CLK and
R/R inputs incorporate dual internal 50
W
termination resistors and
will accept LVPECL, CML, LVDS logic levels.
When Clock transitions from logic Low to High, Data will be
transferred to the differential CML outputs. The differential Clock
inputs allow the NB7V52M to also be used as a negative edge
triggered device.
The 16 mA differential CML outputs provide matching internal
50
W
termination and produce 400 mV output swings when externally
receiver terminated with a 50
W
resistor to V
CC
.
The NB7V52M is offered in a low profile 3 mm x 3 mm 16−pin
QFN package. The NB7V52M is a member of the GigaComm™
family of high performance clock products. Application notes,
models, and support documentation are available at
www.onsemi.com.
Features
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
•
•
•
•
•
•
•
VTD
D
D
VTD
Maximum Input Clock Frequency > 10 GHz
Maximum Input Data Rate > 10 Gb/s
Random Clock Jitter < 0.8 ps RMS, Max
200 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV Peak−to−Peak, Typical
Operating Range: V
CC
= 1.71 V to 2.625 V with V
EE
= 0 V
Internal 50
W
Input Termination Resistors
QFN−16 Package, 3mm x 3mm
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
D Flip−Flop
VTCLK
CLK
CLK
VTCLK
VTR
R R
VTR
Q
Q
RESET
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 4
Publication Order Number:
NB7V52M/D
NB7V52M
VTR
16
VTD
D
D
VTD
R
15
R
14
VTR
13
VCC
Q
Q
VEE
Exposed Pad (EP)
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
R
H
L
D
x
L
H
CLK
x
Z
Z
Q
L
L
H
1
2
NB7V52M
3
4
12
11
10
9
L
Z = LOW to HIGH Transition
x = Don’t care
5
VTCLK
6
7
8
CLK CLK VTCLK
Figure 2. Pin Configuration
(Top View)
Table 1. Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
−
Name
VTD
D
D
VTD
VTCLK
CLK
CLK
VTCLK
VEE
Q
Q
VCC
VTR
R
R
VTR
EP
I/O
−
LVPECL, CML,
LVDS Input
LVPECL, CML,
LVDS Input
−
−
LVPECL, CML,
LVDS Input
LVPECL, CML,
LVDS Input
−
−
CML Output
CML Output
−
−
LVPECL, CML,
LVDS Input
LVPECL, CML,
LVDS Input
−
−
Internal 50
W
Termination Pin for D
Noninverted Differential Data Input. (Note 1)
Inverted Differential Data Input. (Note 1)
Internal 50
W
Termination Pin for D
Internal 50
W
Termination Pin for CLK
Noninverted Differential Clock Input. (Note 1)
Inverted Differential Clock Input. (Note 1)
Internal 50
W
Termination Pin for CLK
Negative Supply Voltage. (Note 2)
Inverted Differential Output
Noninverted Differential Output
Positive Supply Voltage. (Note 2)
Internal 50
W
Termination Pin for R
Noninverted Asynchronous Differential Reset Input. (Note 1)
Inverted Asynchronous Differential Reset Input. (Note 1)
Internal 50
W
Termination Pin for R
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to the die, and must be electrically and thermally con-
nected to VEE on the PC board.
Description
1. In the differential configuration when the input termination pins (VTx, VTx) are connected to a common termination voltage or left open, and
if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation.
2. All VCC and VEE pins must be externally connected to a power supply for proper operation.
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NB7V52M
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
16−QFN
Oxygen Index: 28 to 34
Value
> 2 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
173
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
IO
V
INPP
I
OUT
I
IN
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input/Output Voltage
Differential Input Voltage |CLK − CLK|, |D − D|,
|R − R|
Output Current Through R
TOUT
(50
W
Resistor)
Input Current Through R
TIN
(50
W
Resistor)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 3)
Thermal Resistance (Junction−to−Case) (Note 3)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
QFN−16
QFN−16
QFN−16
Continuous
Surge
Condition 1
V
EE
= 0 V
V
EE
= 0 V
−0.5
v
VIO
v
VCC + 0.5
Condition 2
Rating
3.0
−0.5 to V
CC
+0.5
1.89
34
40
$40
−40 to +85
−65 to +150
42
35
4
265
Unit
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7V52M
Table 4. DC CHARACTERISTICS, Multi−Level Inputs
V
CC
= 1.71 V to 2.625 V, V
EE
= 0 V, T
A
= −40°C to +85°C (Note 4)
Symbol
POWER SUPPLY CURRENT
I
CC
Power Supply Current (Inputs and Outputs Open)
V
CC
= 2.5 V
V
CC
= 1.8 V
90
70
110
90
mA
Characteristic
Min
Typ
Max
Unit
CML OUTPUTS
V
OH
Output HIGH Voltage (Note 5)
V
CC
= 2.5 V
V
CC
= 1.8 V
V
OL
Output LOW Voltage (Note 5)
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
– 30
2470
1770
V
CC
– 650
1850
V
CC
– 600
1200
V
CC
– 10
2490
1790
V
CC
– 500
2000
V
CC
– 450
1350
V
CC
2500
1800
V
CC
– 400
2100
V
CC
– 350
1450
mV
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED
(Note 6) (Figures 5 and 7)
V
th
V
IH
V
IL
V
ISE
Input Threshold Reference Voltage Range (Note 7)
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
Single−Ended Input Voltage (V
IH
− V
IL
)
1000
V
th
+ 100
V
EE
200
V
CC
− 100
V
CC
V
th
− 100
1200
mV
mV
mV
mV
DIFFERENTIAL D/D, CLK/CLK, R/R INPUTS DRIVEN DIFFERENTIALLY
(Figures 6 and 8) (Note 8)
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
− V
ILD
)
Input Common Mode Range (Differential Configuration, Note 9)
(Figure 10)
Input HIGH Current (VT
x
/VT
x
Open)
Input LOW Current (VT
x
/VT
x
Open)
1100
V
EE
100
1050
−250
−250
V
CC
V
CC
− 100
1200
V
CC
− 50
250
250
mV
mV
mV
mV
mA
mA
TERMINATION RESISTORS
R
TIN
R
TOUT
Internal Input Termination Resistor
Internal Output Termination Resistor
45
45
50
50
55
55
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V
CC
.
5. CML outputs loaded with 50
W
to V
CC
for proper operation.
6. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
9. V
CMR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential input
signal.
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NB7V52M
Table 5. AC CHARACTERISTICS
V
CC
= 1.71 V to 2.625 V; V
EE
= 0 V; T
A
= −40°C to 85°C (Note 10)
Symbol
f
MAX
f
DATA MAX
V
OUTPP
t
PLH
,
t
PHL
t
S
t
H
t
RR
t
PW
t
JITTER
V
INPP
t
r,
, t
f
Characteristic
Maximum Input Clock Frequency
Maximum Input Data Rate (PRBS23)
Output Voltage Amplitude (@ V
INPPmin
)
(See Figures 3 and 10, Note 11)
Propagation Delay to Differential Outputs, @ 1 GHz,
Measured at Differential Cross−point
Setup Time (D to CLK)
Hold Time (D to CLK)
Reset Recovery
Minimum Pulse Width
RJ – Output Random Jitter (Note 12)
Input Voltage Swing (Differential Configuration) (Note 13)
Output Rise/Fall Times @ 1 GHz (20% − 80%),
Q, Q
R/R
f
in
v
10 GHz
100
20
35
fin
≤
7 GHz
fin
≤
10 GHz
CLK/CLK to Q/Q
R/R to Q/Q
40
50
275
1
0.2
0.8
1200
50
Min
10
10
300
250
Typ
12
12
400
400
200
300
15
20
200
350
600
Max
Unit
GHz
Gbps
mV
ps
ps
ps
ps
ns
ps RMS
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured using a 400 mV V
INPP
source, 50% duty cycle clock source. All output loading with external 50
W
to V
CC
. Input edge rates
w40
ps (20% − 80%).
11. Output voltage swing is a single−ended measurement operating in differential mode.
12. Additive RMS jitter with 50% duty cycle clock signal.
13. Input voltage swing is a single−ended measurement operating in differential mode.
500
OUTPUT VOLTAGE AMPLITUDE
(mV)
450
Q/Q Output
400
D
350
I
300
D
250
200
0
1
2
3
4
5
6
7
8
9
10
11 12
fin, Clock Input Frequency (GHz)
VTD
50
W
R
TIN
V
CC
VTD
50
W
R
TIN
R
C
R
C
Figure 3. Clock Output Voltage Amplitude
(V
OUTPP
) vs. Input Frequency (f
in
) at Ambient
Temperature (Typ)
Figure 4. Simplified Input Structure
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