INTEGRATED CIRCUITS
74ABT899
9-bit dual latch transceiver with 8-bit
parity generator/checker (3-State)
Product specification
Supersedes data of 1993 Oct 04
IC23 Data Handbook
1998 Jan 16
Philips
Semiconductors
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
FEATURES
•
Symmetrical (A and B bus functions are identical)
•
Selectable generate parity or ”feed-through” parity for A-to-B and
B-to-A directions
DESCRIPTION
The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate
transparent latches for the A bus and B bus. Either bus can
generate or check parity. The parity bit can be fed-through with no
change or the generated parity can be substituted with the SEL
input.
Parity error checking of the A and B bus latches is continuously
provided with ERRA and ERRB, even with both buses in 3-State.
The 74ABT899 features independent latch enables for the A and B
bus latches, a select pin for ODD/EVEN parity, and separate error
signal output pins for checking parity.
•
Independent transparent latches for A-to-B and B-to-A directions
•
Selectable ODD/EVEN parity
•
Continuously checks parity of both A bus and B bus latches as
ERRA and ERRB
•
Ability to simultaneously generate and check parity
•
Can simultaneously read/latch A and B bus data
•
Output capability: +64 mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
FUNCTIONAL DESCRIPTION
The 74ABT899 has three principal modes of operation which are
outlined below. All modes apply to both the A-to-B and B-to-A
directions.
Transparent latch, Generate parity, Check A and B bus parity:
Bus A (B) communicates to Bus B (A), parity is generated and
passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are
High and the Mode Select (SEL) is Low, the parity generated from
A0-A7 and B0-B7 can be checked and monitored by ERRA and
ERRB. (Fault detection on both input and output buses.)
Transparent latch, Feed-through parity, Check A and B bus
parity:
Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL
is High. Parity is still generated and checked as ERRA and ERRB
and can be used as an interrupt to signal a data/parity bit error to the
CPU.
Latched input, Generate/Feed-through parity, Check A (and B)
bus parity:
Independent latch enables (LEA and LEB) allow other permutations of:
•
Power up 3-State
•
Power-up reset
•
Live insertion/extraction permitted
•
Transparent latch / 1 bus latched / both buses latched
•
Feed-through parity / generate parity
•
Check in bus parity / check out bus parity / check in and out bus
parity
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
Propagation delay
An to Bn or Bn to An
Propagation delay
An to ERRA
Input capacitance
Output capacitance
Total supply current
PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled; V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
2.9
6.1
4
7
50
UNIT
ns
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
28-Pin Plastic PLCC
28-Pin Plastic SOP
28-Pin Plastic SSOP
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT899 A
74ABT899 D
74ABT899 DB
NORTH AMERICA
74ABT899 A
74ABT899 D
74ABT899 DB
DWG NUMBER
SOT261-3
SOT136-1
SOT341-1
1998 Jan 16
2
853-1623 18864
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
PIN CONFIGURATION
ODD/EVEN
ERRA
LEA
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
TOP VIEW
8
9
21
20
19
18
17
16
15
B5
B6
28
27
26
25
24
23
22
V
CC
OEB
B0
B1
PLCC PIN CONFIGURATION
B1 B2 B3 B4 B5 B6 B7
25 24 23 22 21 20 19
B0 26
18 BPAR
17 LEB
16 SEL
15 ERRB
14 GND
13 OEA
12 APAR
B2
OEB 27
B3
B4
V
CC
28
ODD/ 1
EVEN
ERRA 2
LEA
3
4
A6 10
A7 11
APAR 12
OEA 13
GND 14
B7
A0
BPAR
LEB
SEL
ERRB
5
6
7
8
9
10
11
A1 A2 A3 A4 A5 A6 A7
SA00289
SA00291
PIN DESCRIPTION
SYMBOL
PIN
NUMBER
4, 5, 6, 7,
8, 9, 10,
11
19, 20,
21, 22,
23, 24,
25, 26
12
18
1
13, 27
16
3, 17
2, 15
14
28
NAME AND FUNCTION
LOGIC SYMBOL
A0 - A7
Latched A bus 3-State inputs/outputs
4
5
6
7
8
9
10 11
12
A0 A1 A2 A3 A4 A5 A6 A7 APAR
B0 - B7
Latched B bus 3-State inputs/outputs
3
17
LEA
LEB
SEL
ODD/EVEN
OEB
OEA
B0 B1 B2 B3 B4 B5 B6 B7 BPAR
ERRA
ERRB
2
15
APAR
BPAR
ODD/
EVEN
OEA, OEB
SEL
LEA, LEB
ERRA,
ERRB
GND
V
CC
A bus parity 3-State input
B bus parity 3-State input
Parity select input (Low for EVEN
parity)
Output enable inputs (gate A to B,
B to A)
Mode select input (Low for generate)
Latch enable inputs (transparent High)
Error signal outputs (active-Low)
Ground (0V)
Positive supply voltage
16
1
27
13
26 25 24 23 22 21 20 19
18
SA00290
1998 Jan 16
3
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
OE
9–bit
Transparent
Latch
27
OEB
9–bit
Output
Buffer
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
3
4
5
6
7
8
9
10
11
12
LE
Parity
Generator
1
mux
0
26
25
24
23
22
21
20
19
18
9–bit
Transparent
Latch
9–bit
Output
Buffer
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
OEA
13
OE
1
mux
0
Parity
Generator
LE
17
LEB
2
ERRA
SEL
16
15
ERRB
ODD/
EVEN
1
SA00292
FUNCTION TABLE
INPUTS
OEB
H
H
H
H
H
H
L
L
L
L
L
L
OEA
H
L
L
L
L
L
H
H
H
H
H
L
SEL
X
L
L
L
H
H
L
L
L
H
H
X
LEA
X
L
H
X
X
H
H
H
L
H
H
X
LEB
X
H
H
L
H
H
X
H
X
L
H
X
3-State A bus and B bus (input A & B simultaneously)
B
→
A, transparent B latch, generate parity from B0 - B7, check B bus parity
B
→
A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
B
→
A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
B
→
A, transparent B latch, parity feed-through, check B bus parity
B
→
A, transparent A & B latch, parity feed-through, check A & B bus parity
A
→
B, transparent A latch, generate parity from A0 - A7, check A bus parity
A
→
B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
A
→
B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
A
→
B, transparent A latch, parity feed-through, check A bus parity
A
→
B, transparent A & B latch, parity feed-through, check A & B bus parity
Output to A bus and B bus (NOT ALLOWED)
OPERATING MODE
H = High voltage level
L = Low voltage level
X = Don’t care
1998 Jan 16
4
Philips Semiconductors
Product specification
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
74ABT899
PARITY AND ERROR FUNCTION TABLE
INPUTS
SEL
H
H
H
H
L
L
L
L
H
L
t
r
*
ODD/EVEN
H
H
L
L
H
H
L
L
xPAR
(A or B)
H
L
H
L
H
L
H
L
Σ
of High
Inputs
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
xPAR
(B or A)
H
H
L
L
H
H
L
L
H
L
H
L
L
H
L
H
OUTPUTS
ERRt
H
L
L
H
L
H
H
L
H
L
L
H
L
H
H
L
ERRr*
H
L
L
H
L
H
H
L
H
H
H
H
H
H
H
H
PARITY MODES
Odd
Mode
Feed-through/check parity
Even
Mode
Odd
Mode
Generate parity
Even
Mode
= High voltage level
= Low voltage level
= Transmit–if the data path is from A→B then ERRt is ERRA
= Receive–if the data path is from A→B then ERRr is ERRB
Blocked if latch is not transparent
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jan 16
5
FPGA/CPLD
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