73M1822/73M1922 MicroDAA
Silicon DAA with Serial Interface
Simplifying System Integration™
DS_1x22_001
DESCRIPTION
The 73M1822 MicroDAA is the world’s first
single-package silicon Data Access Arrangement
(DAA) for data/fax modem and voice applications.
It provides a serial Modem Analog Front End
(MAFE) interface to popular DSP/host processors to
implement a globally compliant low-cost soft modem
solution.
The 73M1822 MicroDAA is available as a
two-chip configuration (the 73M1922) that consists
of a 73M1902 Host-Side Device and a 73M1912
Line-Side Device. The MicroDAA integrates all
codec and DAA functions necessary to achieve
reliable PSTN connection worldwide.
The MicroDAA uses a small pulse transformer,
which can achieve more than 6 kV isolation. Power
may be supplied along with data through this barrier
interface to achieve superior performance in weak
loop current conditions. Inherently immune to RFI
and other forms of common mode interference, the
patented MicroDAA technology achieves global DAA
compliance with unparalleled flexibility, reliability,
and cost structure and requires less than 2 square
inches of a single sided PCB.
The MicroDAA supports Caller ID Type I and II, ring
detection, tip/ring polarity reversal detection, hook
switch control, pulse dialing, regulation of loop
current (DC mask), configurable line impedance
matching, line in use and parallel pickup detection.
The MicroDAA integrates billing tone filters, external
clock reference, audio monitor output, and requires
only a small number of low cost and commonly
available external components.
The MicroDAA incorporates a configurable sample
rate circuit to support soft modem and
DSP-based implementations of all speeds up to
V.92 (56 Kbps). Sampling rates from 7.2 kHz to
16 kHz can be easily supported.
APPLICATIONS
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V.92 modems
Satellite Set Top Boxes
Fax/Multifunction Peripherals (MFP)
Point of Sale Terminals
Voicemail Systems
Industrial and medical telemetry
DATA SHEET
April 2010
FEATURES
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Meets FCC, ETSI ES 203 021-2, JATE, NET4
and other PTT standards
Configurable PSTN termination
Up to 8 mA minimum line current operation
0 dBm Transmit/Receive full scale
THD –80 dB
16-bit codec up to 16 kHz sample rate
Up to 56 Kbps (V.92) performance
Configurable sample rates (7.2 – 16 kHz)
Reference clock range of 9-40 MHz
Crystal frequency range of 9-27 MHz
MAFE I/F with Master, Slave and Daisy
Chaining
Billing tone reject filter
Polarity reversal detection on-chip
GPIO for user-configurable I/O port
Call Progress Monitor
3.3 V Operation
Industrial temperature range (-40° to +85° C)
6 kV isolation (73M1922)
4-5 kV isolation (73M1822)
8x8 mm 42-pin QFN (73M1822)
20-pin TSSOP or 5x5 mm 32-pin QFN
(73M1922)
RoHS compliant (6/6) lead-free package
Rev. 1.6
© 2010 Teridian Semiconductor Corporation
1
73M1822/73M1922 Data Sheet
DS_1x22_001
Table of Contents
1
2
Introduction ...................................................................................................................................... 6
Pinout ................................................................................................................................................ 8
2.1
73M1902 20-Pin TSSOP Pinout ............................................................................................... 8
2.2
73M1912 20-Pin TSSOP Pinout ............................................................................................. 10
2.3
73M1902 32-Pin QFN Pinout ................................................................................................. 11
2.4
73M1912 32-Pin QFN Pinout ................................................................................................. 13
2.5
73M1822 Pinout..................................................................................................................... 15
2.6
Exposed Bottom Pad on 73M1x66B QFN Packages .............................................................. 16
Electrical Characteristics and Specifications................................................................................ 17
3.1
Isolation Barrier Characteristics.............................................................................................. 17
3.2
Electrical Specifications ......................................................................................................... 17
3.2.1 Absolute Maximum Ratings .......................................................................................... 17
3.2.2 Recommended Operating Conditions ........................................................................... 17
3.2.3 DC Characteristics........................................................................................................ 18
3.3
Serial Interface Timing Specification ...................................................................................... 19
3.4
Analog Specifications............................................................................................................. 19
3.4.1 DC Specifications ......................................................................................................... 19
3.4.2 Call Progress Monitor ................................................................................................... 20
3.5
73M1x22 Line-Side Electrical Specifications (73M1912)......................................................... 22
3.6
Reference and Regulation ..................................................................................................... 22
3.7
AC Signal Levels ................................................................................................................... 22
3.8
DC Transfer Characteristics ................................................................................................... 23
3.9
Transmit Path ........................................................................................................................ 24
3.10 Receive Path ......................................................................................................................... 25
3.11 Transmit Hybrid Cancellation ................................................................................................. 26
3.12 Receive Notch Filter............................................................................................................... 26
3.13 Detectors ............................................................................................................................... 27
3.13.1 Over-Voltage Detector................................................................................................. 27
3.13.2 Over-Current Detector ................................................................................................. 27
3.13.3 Under-Voltage Detector............................................................................................... 27
3.13.4 Over-Load Detector..................................................................................................... 27
Applications Information ................................................................................................................ 28
4.1
Example Schematic of the 73M1922 and 73M1822 ................................................................ 28
4.2
Bill of Materials ...................................................................................................................... 30
4.3
Over-Voltage and EMI Protection ........................................................................................... 31
4.4
Isolation Barrier Pulse Transformer ........................................................................................ 32
Control and Status Registers ......................................................................................................... 33
5.1
Line-Side Device Register Polling .......................................................................................... 36
Hardware Control Functions .......................................................................................................... 37
6.1
Device Revision ..................................................................................................................... 37
6.2
Interrupt Control..................................................................................................................... 37
6.3
Power Management ............................................................................................................... 38
6.4
Device Clock Management .................................................................................................... 38
6.5
GPIO Registers...................................................................................................................... 39
6.6
Call Progress Monitor ............................................................................................................ 40
Clock and Sample Rate Management ............................................................................................ 41
7.1
Clock Generation with HIC (73M1902) ................................................................................... 41
7.2
Crystal Oscillator.................................................................................................................... 41
7.3
PLL Prescaler ........................................................................................................................ 42
7.4
PLL Circuit ............................................................................................................................. 42
7.5
PLL System Timing Control.................................................................................................... 45
MAFE Serial Interface ..................................................................................................................... 46
8.1
Data and Control Frame Formats ........................................................................................... 46
8.2
Data and Control Frame Timing ............................................................................................. 47
8.3
Serial Clock Operation ........................................................................................................... 48
Rev 1.6
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2
DS_1x22_001
73M1822/73M1922 Data Sheet
8.4
MicroDAA IN Master/Slave Configuration ............................................................................... 49
8.5
73M1x22 Reset ..................................................................................................................... 49
8.6
73M1x22 in Daisy Chain Configuration................................................................................... 50
8.7
MAFE Configuration Registers ............................................................................................... 51
8.8
Slave Registers...................................................................................................................... 51
9
Signal Processing........................................................................................................................... 52
9.1
Transmit Path Signal Processing ........................................................................................... 52
9.1.1 General Description ...................................................................................................... 52
9.1.2 Total Transmit Path Response...................................................................................... 52
9.1.3 73M1x22 Transmit Spectrum ........................................................................................ 53
9.2
Receive Path Signal Processing ............................................................................................ 53
9.2.1 General Description ...................................................................................................... 53
9.2.2 Total Receive Path Response....................................................................................... 54
9.3
Signal Control Functions ........................................................................................................ 55
9.3.1 Transmit and Receive Level Control ............................................................................. 55
10 Barrier Information ......................................................................................................................... 57
10.1 Isolation Barrier...................................................................................................................... 57
10.2 Barrier Powered Options ........................................................................................................ 57
10.2.1 Barrier Powered Operation .......................................................................................... 57
10.2.2 Line Powered Operations ............................................................................................ 57
10.3 Synchronization of the Barrier ................................................................................................ 57
10.4 Auxiliary A/D Converter .......................................................................................................... 58
10.5 Auto-Poll................................................................................................................................ 58
10.6 Barrier Control Functions ....................................................................................................... 59
10.7 Line-Side Device Operating Modes ........................................................................................ 60
10.8 Fail-Safe Operation of the Line-Side Device ........................................................................... 60
11 Configurable Direct Access Arrangement (DAA) .......................................................................... 61
11.1 Pulse Dialing.......................................................................................................................... 61
11.2 DC Termination...................................................................................................................... 61
11.2.1 Current Limit Detection................................................................................................ 63
11.3 AC Termination ...................................................................................................................... 63
11.4 Billing Tone Rejection ............................................................................................................ 64
11.5 Trans-Hybrid Cancellation ...................................................................................................... 65
11.6 Direct Access Arrangement Control Functions ....................................................................... 65
11.7 International Register Settings Table for DC and AC Terminations ......................................... 69
12 Line Sensing and Status ................................................................................................................ 70
12.1 Auxiliary A/D Converter .......................................................................................................... 70
12.2 Ring Detection ....................................................................................................................... 70
12.3 Line In Use Detection (LIU) .................................................................................................... 70
12.4 Parallel Pick Up (PPU) ........................................................................................................... 70
12.5 Polarity Reversal Detection .................................................................................................... 70
12.6 Off-hook Detection of Caller ID Type II ................................................................................... 70
12.7 Voltage and Current Detection ............................................................................................... 71
12.8 Under Voltage Detection (UVD) ............................................................................................. 71
12.9 Over Voltage Detection (OVD) ............................................................................................... 71
12.10 AC Signal Over Load Detection.............................................................................................. 71
12.11 Over Current Detection (OID)................................................................................................. 71
12.12 Line Status Functions Control Functions ................................................................................ 72
13 Loopback and Testing Modes ........................................................................................................ 75
14 Performance ................................................................................................................................... 77
14.1 DC VI Characteristics ............................................................................................................. 77
14.2 Receive ................................................................................................................................. 78
15 Package Layout .............................................................................................................................. 79
16 Ordering Information ...................................................................................................................... 81
17 Contact Information........................................................................................................................ 81
Revision History ..................................................................................................................................... 82
Rev. 1.6
3
73M1822/73M1922 Data Sheet
DS_1x22_001
Figures
Figure 1: Simple 73M1x22 Reference Block Diagram.................................................................................. 6
Figure 2: 73M1902 20-Pin TSSOP Pinout ................................................................................................... 8
Figure 3: 73M1912 20-Pin TSSOP Pinout ................................................................................................. 10
Figure 4: 73M1902 32-Pin QFN Pinout ..................................................................................................... 11
Figure 5: 73M1912 32-Pin QFN Pinout ..................................................................................................... 13
Figure 6: 73M1822 42-Pin Pinout.............................................................................................................. 15
Figure 7: MAFE Timing Diagram ............................................................................................................... 19
Figure 8: Call Progress Monitor Frequency Response............................................................................... 20
Figure 9: Demo Board Circuit Connecting AOUT to a Speaker .................................................................. 20
Figure 10: Recommended Circuit for the 73M1922 ................................................................................... 28
Figure 11: Recommended Circuit for the 73M1822 ................................................................................... 29
Figure 12: Suggested Over-voltage Protection and EMI Suppression Circuit ............................................. 31
Figure 13: Clock Generation Block Diagram (assumes 8 kHz sample rate) ............................................... 41
Figure 14: Crystal Oscillator with Configurable Load Current..................................................................... 41
Figure 15: Prescaler Block Diagram .......................................................................................................... 42
Figure 16: PLL Block Diagram .................................................................................................................. 42
Figure 17: Serial Port Timing Diagram ...................................................................................................... 46
Figure 18: Data and Control Frames Timing Diagram................................................................................ 47
Figure 19: Control Frame Position versus SPOS....................................................................................... 48
Figure 20: SCLK and
FS
with SCKM = 0................................................................................................... 48
Figure 21: Example Connections for Master and Slave Operation ............................................................. 49
Figure 22: Master/Slave Serial Timing Diagram ........................................................................................ 49
Figure 23: Daisy Chaining a Master and Two Slaves ................................................................................ 50
Figure 24: Timing Diagram with One Master and Two Slaves .................................................................... 50
Figure 25: Transmit Path Overall Frequency Response to Fs (8 kHz)........................................................ 52
Figure 26: Pass-Band Response of the Transmit Path .............................................................................. 52
Figure 27: Transmit Spectrum to 32 kHz ................................................................................................... 53
Figure 28: Overall Frequency Response of the Receive Path .................................................................... 54
Figure 29: Pass-band Response of the Overall Receive Path.................................................................... 54
Figure 30: Line-Side Device AC and DC Circuits....................................................................................... 60
Figure 31: DC-IV Characteristics............................................................................................................... 61
Figure 32: Tip-Ring Voltage versus Current Using Different DCIV Settings................................................ 62
Figure 33: Voltage versus Current in the Seize Mode is the Same for All DCIV Settings ............................ 63
Figure 34: Magnitude Response of IPMF, ACZ=01 (ETSI ES 203 021-2) .................................................. 64
Figure 35: Magnitude Response of Billing Tone Notch Filter ..................................................................... 64
Figure 36: Loopback Modes Highlighted ................................................................................................... 75
Figure 37: Off-Hook Tip and Ring DC Characteristics................................................................................ 77
Figure 38: ES 203 021-2 DC Mask with Current Limit Enabled .................................................................. 77
Figure 39: Australian Hold State Characteristics ....................................................................................... 78
Figure 40: Return Loss ............................................................................................................................. 78
Figure 41: 20-Pin TSSOP Package Dimensions........................................................................................ 79
Figure 42: 32-Pin QFN Package Dimensions ............................................................................................ 79
Figure 43: 42-Pin QFN Package Dimensions ............................................................................................ 80
4
Rev. 1.6
DS_1x22_001
73M1822/73M1922 Data Sheet
Tables
Table 1: 73M1902 20-Pin TSSOP Pin Definitions ........................................................................................ 8
Table 2: 73M1912 20-Pin TSSOP Pin Definitions ...................................................................................... 10
Table 3: 73M1902 32-Pin QFN Pin Definitions .......................................................................................... 11
Table 4: 73M1912 32-Pin QFN Pin Definitions .......................................................................................... 13
Table 5: 73M1822 Pin Definitions ............................................................................................................. 15
Table 6: Isolation Barrier Characteristics at 8 kHz Sample Rate ................................................................ 17
Table 7: Absolute Maximum Device Ratings ............................................................................................. 17
Table 8: Recommended Operating Conditions .......................................................................................... 17
Table 9: DC Characteristics ...................................................................................................................... 18
Table 10: Serial Data Port Timing at 8 kHz Sample Rate........................................................................... 19
Table 11: Reference Voltage Specifications .............................................................................................. 19
Table 12: Component Values for the Speaker Driver ................................................................................. 20
Table 13: Call Progress Monitor Specification ........................................................................................... 21
Table 14: Line-Side Absolute Maximum Ratings ....................................................................................... 22
Table 15: VBG Specifications ................................................................................................................... 22
Table 16: Maximum Transmit Levels ......................................................................................................... 22
Table 17: Maximum DC Transmit Levels ................................................................................................... 23
Table 18: Transmit Path............................................................................................................................ 24
Table 19: Receive Path ............................................................................................................................ 25
Table 20: Transmit Hybrid Cancellation Characteristics ............................................................................. 26
Table 21: Receive Notch Filter .................................................................................................................. 26
Table 22: Over-Voltage Detector............................................................................................................... 27
Table 23: Over-Current Detector ............................................................................................................... 27
Table 24: Under-Voltage Detector ............................................................................................................. 27
Table 25: Over-Load Detector ................................................................................................................... 27
Table 26: Reference Bill of Materials for 73M1822/73M1922..................................................................... 30
Table 27: Reference Bill of Materials for Figure 12 .................................................................................... 31
Table 28: Compatible Pulse Transformer Sources .................................................................................... 32
Table 29: Transformer Characteristics ...................................................................................................... 32
Table 30: Control and Status Register Map ............................................................................................... 33
Table 31: Alphabetical Bit Map ................................................................................................................. 34
Table 32: Clock Generation Register Settings for Fxtal = 27 MHz ............................................................. 43
Table 33: Clock Generation Register Settings for Fxtal = 24.576 MHz....................................................... 43
Table 34: Clock Generation Register Settings for Fxtal = 9.216 MHz......................................................... 43
Table 35: Clock Generation Register Settings for Fxtal = 24.000 MHz....................................................... 44
Table 36: Clock Generation Register Settings for Fxtal = 25.35 MHz......................................................... 44
Table 37: PLL System Timing Controls ..................................................................................................... 45
Table 38: Behavior of SCLK under SCKM................................................................................................. 48
Table 39: Signal Control Functions ........................................................................................................... 55
Table 40: Transmit Gain Control ............................................................................................................... 55
Table 41: Receive Gain Control ................................................................................................................ 56
Table 42: Barrier Control Functions........................................................................................................... 59
Table 43: Trans-Hybrid Cancellation ......................................................................................................... 65
Table 44: DAA Control Functions .............................................................................................................. 65
Table 45: Recommended Register Settings for International Compatibility ................................................ 69
Table 46: Line Sensing Control Functions ................................................................................................. 72
Table 47: Loopback Modes....................................................................................................................... 75
Table 48: Loopback Controls .................................................................................................................... 76
Table 49: Order Numbers and Packaging Marks ....................................................................................... 81
Rev. 1.6
5
FPGA/CPLD
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