CY7C107D
CY7C1007D
1-Mbit (1 M × 1) Static RAM
1-Mbit (1 M × 1) Static RAM
Features
■
■
Functional Description
The CY7C107D
[1]
and CY7C1007D
[1]
are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy
memory expansion is provided by an active LOW Chip Enable
(CE) and tri-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when deselected. The output pin (D
OUT
) is placed in a
high-impedance state when:
■
■
Pin- and function-compatible with CY7C107B/CY7C1007B
High speed
❐
t
AA
= 10 ns
Low active power
❐
I
CC
■
= 80 mA @ 10 ns
■
Low complementary metal oxide semiconductor (CMOS)
standby power
❐
I
SB2
= 3 mA
Deselected (CE HIGH)
When the write operation is active (CE and WE LOW)
■
■
■
■
■
2.0 V data retention
Automatic power-down when deselected
CMOS for optimum speed/power
Transistor transistor logic (TTL) compatible inputs and outputs
CY7C107D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1007D available in Pb-free 28-pin 300-Mil
wide Molded SOJ package
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the input pin (D
IN
) is written into the
memory location specified on the address pins (A
0
through A
19
).
Read from the device by taking Chip Enable (CE) LOW while
while forcing Write Enable (WE) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins appears on the data output (D
OUT
) pin.
The CY7C107D and CY7C1007D devices are suitable for
interfacing with processors that have TTL I/P levels. It is not
suitable for processors that require CMOS I/P levels. Please see
Electrical Characteristics on page 4
for more details and
suggested alternatives.
For a complete list of related documentation,
click here.
Logic Block Diagram
DIN
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE
WE
INPUT BUFFER
ROW DECODER
1M x 1
ARRAY
SENSE AMPS
DOUT
COLUMN DECODER
POWER
DOWN
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
www.cypress.com.
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
Cypress Semiconductor Corporation
Document Number: 38-05469 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 24, 2014
CY7C107D
CY7C1007D
Contents
Pin Configuration ............................................................. 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Document Number: 38-05469 Rev. *K
Page 2 of 15
CY7C107D
CY7C1007D
Pin Configuration
Figure 1. 28-pin SOJ pinout (Top View)
[2]
A
10
A
11
A
12
A
13
A
14
A
15
NC
A
16
A
17
A
18
A
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
9
A
8
A
7
A
6
A
5
A
4
NC
A
3
A
2
A
1
A
0
D
IN
CE
D
OUT
WE
GND
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current, I
SB2
CY7C107D-10
CY7C1007D-10
10
80
3
Unit
ns
mA
mA
Note
2. NC pins are not connected on the die.
Document Number: 38-05469 Rev. *K
Page 3 of 15
CY7C107D
CY7C1007D
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature
65
°C to +150 °C
Ambient temperature with
power applied
55
°C to +125 °C
Supply voltage on
V
CC
relative to GND
[3]
0.5
V to +6.0 V
DC voltage applied to outputs
in High-Z state
[3]
0.5
V to V
CC
+ 0.5 V
DC input voltage
[3]
0.5
V to V
CC
+ 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Range
Industrial
Ambient
Temperature
–40 °C to +85 °C
V
CC
5 V
0.5 V
Speed
10 ns
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
[3]
Input leakage current
Output leakage current
V
CC
operating supply current
GND < V
I
< V
CC
GND < V
I
< V
CC
, output disabled
V
CC
= Max, I
OUT
= 0 mA,
f = f
max
= 1/t
RC
100 MHz
83 MHz
66 MHz
40 MHz
I
SB1
I
SB2
Automatic CE Power-down
current – TTL Inputs
Automatic CE Power-down
current – CMOS Inputs
Max V
CC
, CE > V
IH
,
V
IN
>V
IH
or V
IN
< V
IL
, f = f
max
Max V
CC
, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V, f = 0
I
OH
=
4.0
mA
I
OH
=
0.1
mA
I
OL
= 8.0 mA
Test Conditions
7C107D-10
7C1007D-10
Min
2.4
–
2.2
0.5
1
–1
Max
3.4
[4]
0.4
V
CC
+ 0.5
0.8
+1
+1
80
72
58
37
10
3
V
V
V
A
A
mA
mA
mA
mA
mA
mA
V
Unit
Note
3. V
IL
(min) = –2.0 V and V
IH
(max) = V
CC
+ 1 V for pulse durations of less than 5 ns.
4. Please note that the maximum V
OH
limit does not exceed minimum CMOS VIH of 3.5V. If you are interfacing this SRAM with 5 V legacy processors that require
a minimum V
IH
of 3.5 V, please refer to Application Note
AN6081
for technical details and options you may consider.
Document Number: 38-05469 Rev. *K
Page 4 of 15
CY7C107D
CY7C1007D
Capacitance
Parameter
C
IN
: Controls
C
OUT
Output capacitance
[5]
Description
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= 5.0 V
Max
7
10
10
Unit
pF
pF
pF
C
IN
: Addresses Input capacitance
Thermal Resistance
Parameter
JA
JC
[5]
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
300-Mil Wide
SOJ
59.16
40.84
400-Mil Wide
SOJ
58.76
40.54
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
[6]
ALL INPUT PULSES
90%
10%
90%
10%
Z = 50
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
3.0V
30 pF*
GND
Rise Time:
3
ns
(a)
High-Z characteristics:
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
(b)
Fall Time:
3
ns
R1 480
R2
255
(c)
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) are tested using the load conditions shown in
Figure 2
(a). High-Z characteristics are tested for all speeds using the test load
shown in
Figure 2
(c).
Document Number: 38-05469 Rev. *K
Page 5 of 15
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