NB3N501
3.3V / 5.0V 13 MHz to
160 MHz PLL Clock
Multiplier
Description
The NB3N501 is a clock multiplier that will generate one of nine
selectable output multiples of an input frequency via two 3−level
select inputs (S0, S1). It accepts a standard fundamental mode crystal
or an external reference clock signal. Phase−Locked−Loop (PLL)
design techniques are used to produce a low jitter, TTL level clock
output up to 160 MHz with a 50% duty cycle. An Output Enable (OE)
pin is provided, and when asserted low, the clock output goes into
tri−state (high impedance). The NB3N501 is commonly used in
electronic systems as a cost efficient replacement for crystal
oscillators
Features
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MARKING DIAGRAM
8
1
SOIC−8
D SUFFIX
CASE 751
3N501
A
L
Y
W
G
8
3N501
ALYWG
G
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Clock Output Frequencies up to 160 MHz
Nine Selectable Multipliers of the Input Frequency
Operating Range: V
DD
= 3.3 V
±10%
or 5.0 V
±5%
Low Jitter Output of 25 ps One Sigma (rms)
Zero ppm Clock Multiplication Error
45%
−
55% Output Duty Cycle
TTL/CMOS Output with 25 mA TTL Level Drive
Crystal Reference Input Range of 5
−
27 MHz
Input Clock Frequency Range of 2
−
50 MHz
OE, Output Enable with Tri−State Output
8−Pin SOIC
Industrial Temperature Range
−40°C
to +85°C
These are Pb−Free Devices
V
DD
X1/ICLK
crystal or
clock
C
LX2
C
LX1
X2
Crystal
Oscillator
Multiplier
Select
÷
M
S1 S0
GND
÷
P
Phase
Detector
Charge
Pump
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
VCO
TTL/
CMOS
Output
CLKOUT
Feedback
OE
Figure 1. NB3N501 Logic Diagram
©
Semiconductor Components Industries, LLC, 2013
November, 2013
−
Rev. 2
1
Publication Order Number:
NB3N501/D
NB3N501
Table 1. CLOCK MULTIPLIER SELECT TABLE
S1*
L
L
L
M
M
M
H
H
H
S0*
L
M
H
L
M
H
L
M
H
CLKOUT Multiplier
4X Input
5.3125X Input
5X Input
6.25X Input
2X Input
3.125X Input
6X Input
3X Input
8X Input
S1
4
5
CLKOUT
GND
3
6
X1/CLK
V
DD
1
2
8
7
X2
OE
S0
Figure 2. NB3N501 Package Pinout,
8−Pin (150 mil) SOIC
*Pins S1 and S0 default to M when open
L = GND
H = VDD
M = OPEN (unconnected; will default to VDD/2)
Table 2. PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
Name
X1/CLK
VDD
GND
S1
CLKOUT
S0
OE
X2
I/O
Input
Power supply
Power supply
Three level Input
CMOS/TTL Output
Three level Input
CMOS/TTL Input
Crystal
Description
Crystal or external reference clock input
Positive supply voltage
0 V. Ground.
Multiplier select pin
−
connect to V
DD
, GND or float
Clock output
Multiplier select pin
−
connect to V
DD
, GND or float
Output Enable. CLKOUT is high impedance when OE is low. Internal pullup
Crystal input – Leave open when providing an external clock reference
Table 3. COMMON OUTPUT FREQUENCY
EXAMPLES
Output Frequency
(MHz)
20
24
30
32
33.33
37.5
40
48
50
60
62.5
Input Frequency
(MHz)
10
12
10
16
16.66
12
10
12
16.66
10
20
S1, S0
M, M
M, M
1, M
M, M
M, M
M, 1
0, 0
0, 0
1, M
1, 0
M, 1
Table 3. COMMON OUTPUT FREQUENCY
EXAMPLES
Output Frequency
(MHz)
64
66.66
72
75
80
83.33
90
100
106.25
120
125
Input Frequency
(MHz)
16
16.66
12
12
10
16.66
15
20
20
15
20
S1, S0
0, 0
0, 0
1, 0
M, 0
1, 1
0, 1
1, 0
0, 1
0, M
1, 1
M, 0
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NB3N501
Table 4. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Charged Device Model
SOIC−8
Oxygen Index: 28 to 34
Value
> 1 kV
> 150 V
> 1 kV
Level 1
UL 94 V 0 @ 0.125 in
9727
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
V
DD
V
IO
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Input and Output Voltages
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
(Note 2)
SOIC−8
SOIC−8
SOIC−8
Condition 1
GND = 0 V
Condition 2
Rating
7
−0.5
V
v
V
IO
v
V
DD
+ 0.5
−40
to +85
−65
to +150
190
130
41 to 44
265
Unit
V
V
°C
°C
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB3N501
Table 6. DC CHARACTERISTICS
V
DD
= 3.3 V
±
10% or 5.0 V
±
5% unless otherwise noted, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
V
DD
I
DD
Characteristic
Operating Voltage at 100 MHz (with 20 MHz crystal)
V
CC
= 5 V
V
CC
= 3.3 V
Min
4.75
3.0
20
15
V
DD
−
0.4
2.4
0.4
(V
DD
/ 2) + 1
(V
DD
/ 2)
−
1
V
DD
−
0.5
0.5
2.0
0.8
4
±70
270
20
Typ
Max
5.25
3.6
Unit
V
mA
Power Supply Current – Inputs and outputs open, CLKOUT operating
at 100 MHz (with 20 MHz crystal)
V
CC
= 5 V
V
CC
= 3.3 V
Output HIGH Voltage I
OH
=
−4
mA CMOS High
Output HIGH Voltage I
OH
=
−25
mA TTL High
Output LOW Voltage I
OL
= 25 mA
Input HIGH Voltage, CLK only (pin 1)
Input LOW Voltage, CLK only (pin 1)
Input HIGH Voltage, S0, S1
Input LOW Voltage, S0, S1
Input HIGH Voltage, OE (pin 7)
Input LOW Voltage, OE (pin 7)
Input Capacitance, S0, S1 and OE
Output Short Circuit Current
On Chip Pullup Resistor
Nominal Output Impedance
V
OH
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
C
in
I
SC
RPU
V
V
V
V
V
V
V
V
V
pF
mA
kW
W
3. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors
should be connected from pins X1/CLK to GND and X2 to GND. The value of these capacitors is given by the following equation, where
C
L
is the specified crystal load capacitance: Crystal capacitance (pF) = (C
L
−
5) X 2. So, for a crystal with 16 pF load capacitance, use
two 22 pF capacitors.
Table 7. AC CHARACTERISTICS
V
DD
= 3.3 V
±
10% or 5.0 V
±
5% unless otherwise noted, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
f
Xtal
f
CLKIN
f
OUT
Characteristic
Crystal Input Frequency (Note 4)
Clock Input Frequency
Output Frequency Range f
OUTMIN
≤
f
IN
x Multiplier
≤
f
OUTMAX
V
DD
= 4.75 to 5.25 V (5.0 V
±
5%)
V
DD
= 3.0 to 3.6 V (3.3 V
±
10%)
Output Clock Duty Cycle at V
DD
/ 2
Output enable time, OE high to output on
Output disable time, OE low to tri−state
Period Jitter (rms, 1
s)
Total Period Jitter, (peak−to−peak)
Output rise/fall time (0.8 V to 2.0 V) (measured with 15 pF load)
Min
5
2
13
13
45
50
50
50
25
±70
1
Typ
Max
27
50
160
100
55
Unit
MHz
MHz
MHz
DC
OE
H
OE
L
t
jitter (rms)
t
jitter (pk−to−pk)
t
r
/t
f
%
ns
ns
ps
ps
ns
4. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors
should be connected from pins X1/CLK to GND and X2 to GND. The value of these capacitors is given by the following equation, where
C
L
is the specified crystal load capacitance: Crystal capacitance (pF) = (C
L
−
12) X 2. So, for a crystal with 16 pF load capacitance, use
two 8 pF capacitors.
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NB3N501
APPLICATIONS INFORMATION
High Frequency CMOS/TTL Oscillators
Crystal Load Capacitors
The NB3N501, along with a low frequency fundamental
mode crystal, can build a high frequency TTL output
oscillator. For example, a 20 MHz crystal connected to the
NB3N501 with the 5X output selected (S1 = L, S0 = H)
produces an 100 MHz CMOS/TTL output clock.
Decoupling and External Components
The NB3N501 requires a 0.01
mF
decoupling capacitor to
be connected between V
DD
and GND on pins 2 and 3. It must
be connected close to the NB3N501 to minimize lead
inductance. Control input pins can be connected to device
pins V
DD
or GND, or to the V
DD
and GND planes on the
board.
Series Termination Resistor
A 33
W
terminating resistor can be used next to the CLK
pin for trace lengths over one inch.
ORDERING INFORMATION
Device
NB3N501DG
NB3N501DR2G
Package
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
The total on chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be used.
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors, if needed, must be connected from each of the
pins X1 and X2 to ground. The value (in pF) of these crystal
caps should equal (C
L
−
12 pF) * 2. In this equation, C
L
=
crystal load capacitance in pF. Example: For a crystal with
a 16 pF load capacitance, each crystal capacitor would be
8 pF [(16
−
12) x 2 = 8].
Shipping
†
98 Units / Rail
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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