DATASHEET
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
ICS1894-44
Description
The ICS1894-44 is a low-power, physical-layer device
(PHY) that supports the ISO/IEC 10Base-T and
100Base-TX Carrier-Sense Multiple Access/Collision
Detection (CSMA/CD) Ethernet standards, ISO/IEC
8802.3. It is intended for MII, Node/Repeater applications
and includes the Auto-MDIX feature that automatically
corrects crossover errors in plant wiring.
The ICS1894-44 incorporates Digital-Signal Processing
(DSP) control in its Physical-Medium Dependent (PMD)
sub-layer. As a result, it can transmit and receive data on
unshielded twisted-pair (UTP) category 5 cables with
attenuation in excess of 24 dB at 100MHz.
The ICS1894-44 provides a Serial-Management Interface
for exchanging command and status information with a
Station-Management (STA) entity. The ICS1894-44
Media-Dependent Interface (MDI) can be configured to
provide either half-duplex or full-duplex operation at data
rates of 10 Mb/s or 100Mb/s.
In addition, the ICS1894-44 includes a programmable LED
and interrupt output function. The LED outputs can be
configured through registers to indicate the occurance of
certain events such as LINK, COLLISION, ACTIVITY, etc.
The purpose of the programmable interrupt output is to
notify the PHY controller device immediately when a certain
event happens instead of having the PHY controller
continuously poll the PHY. The events that could be used to
generate interrupts are: receiver error, Jabber, page
received, parallel detect fault, link partner acknowledge, link
status change, auto-negotiation complete, remote fault,
collision, etc.
The ICS1894-44 has deep power modes that can result in
significant power savings when the link is broken.
Applications:
NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines, printers,
network connected appliances, and industrial equipment.
Features
•
Supports category 5 cables and above with attenuation in
excess of 24dB at 100 MHz.
•
Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sub layers functions of IEEE
standard.
•
10Base-T and 100Base-TX IEEE 8802.3 compliant
•
MIIM (MDC/MDIO) management bus for PHY register
configuration
•
Single 3.3V power supply
•
Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full and half-duplex modes
– Loopback mode for Diagnostic Functions
•
•
•
•
•
•
•
Auto-MDI/MDIX crossover correction
Low-power CMOS (typically 300 mW)
Power-Down mode (typically 21mW)
Clock and crystal supported in MII mode
Programmable LEDs
Interrupt output pin
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander
correction
– Transmit wave shaping and stream cipher
scrambler
– MLT-3 encoder and NRZ/NRZI encoder
•
•
•
•
•
Core power supply (3.3 V)
3.3 V/1.8 V VDDIO operation supported
Smart power control with deep power down feature
Available in 40-pin (6mm x 6mm) QFN package, Pb-free
Industrial Temp and Lead Free
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
1
ICS1894-44
REV B 030112
ICS1894-44
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
PHYCEIVER
Block Diagram
100Base-T
10/100 MII
MAC
Interface
Interface
MUX
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Smart Power
Control
Block
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
Pin Assignment
P1/ISO/LED1
P0/LED0
P4/LED2
REFOUT
REFIN
NC
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
VSS
1
31
VDDD
TXD3
TXD2
TXD1
LED3
TXD0
TXEN
SPEED/TXCLK
NOD/RXER
NLG40 Without Ground Connecting to
Thermal Pad
ANSEL/RXCLK
TXER
RTSPEED
RXDV
FDPX/RXD0
11
21
SI/LED4
REGPIN/COL
P2/INT
MDC
40-pin MLF
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
RXTR1/RXD1
HWSW/CRS
MDIO
AMDIX/RXD3
RESET_N
P3/RXD2
VDDIO
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10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
PHYCEIVER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Pin
Name
NC
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
VSS
RESET_N
P2/INT
MDIO
MDC
VDDIO
HWSW/
CRS
Regpin/
COL
AMDIX/RXD3
P3/RXD2
RXTRI/
RXD1
SI/LED4
FDPX/
RXD0
RXDV
RTSPEED
TXER
ANSEL/
RXCLK9
NOD/
RXER
Pin
Type
—
AIO
AIO
Power
AIO
AIO
Power
AIO
Input
IO/Ipd
IO
Input
Power
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipd
Ipu
IN
IO/Ipu
IO/Ipd
No connect.
Pin Description
Twisted pair port A (for either transmit or receive) positive signal
Twisted pair port A (for either transmit or receive) negative signal
3.3V Power Supply
Twisted pair port B (for either transmit or receive) negative signal
Twisted pair port B (for either transmit or receive) positive signal
3.3V Power Supply
Transmit Current bias pin, connected to Vdd and ground via two resistors.
Hardware reset for the whole chip (active low)
PHY address Bit 2 as input (during power on reset and hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
Management Data Input/Output
Management Data Clock
3.3 V IO Power Supply.
Hardware/Software control for phy speed as input (during power on reset and
hardware reset) and CRS output in MII mode.
Full register access enable as input (during power on reset and hardware reset) and
COL output in MII mode
AMDIX hardware enable as input (during power on reset and hardware reset)
Receive data Bit 3 as output in MII mode
PHY address Bit 3 as input (during power on reset and hardware reset)
Receive data Bit 2 as output in MII mode
RX isolate enable (during power on reset and hardware reset)
Received data Bit 1 as output in MII mode.
MII/SI mode select as input (during power on reset and hardware reset) and
LED #4 as output
Full duplex enable (during power on reset and hardware reset)
Received data Bit 0 as output in MII mode.
MII select as input (during power on reset and hardware reset)
Receive data valid in MII mode.
Real-time 10/100M input select. 1 = 100M mode, 0 = 10M mode.
TXER Input
Auto-negotiation enable (during power on reset and hardware reset)
Receive clock as output in MII mode
Node/repeater select (during power on reset and hardware reset)
Receive error as output in MII mode
Ground Connect to ground.
Ground Connect to ground.
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
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10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
PHYCEIVER
Pin
Number
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin
Name
SPEED/
TXCLK
TXEN
TXD0
VDDD
LED3
TXD1
TXT2
TXD3
REFOUT
REFIN
P4/LED2
P0/LED0
P1/ISO/LED1
Pin
Type
IO/Ipu
Input
Input
Power
IO/Ipu
Input
Input
Input
Input
IO/Ipu
IO
IO
Pin Description
10M/100M select as input (during power on reset and hardware reset)
Transmit clock as output in MII mode
Transmit enable for MII mode
Transmit data Bit 0 for MII mode
Core Power Supply
LED3 output
Transmit data Bit 1for MII mode
Transmit data Bit 2 for MII mode
Transmit data Bit 3 for MII mode
25 MHz crystal (or clock) input for MII mode.
PHY address Bit 4 as input (always latched high during power on reset and
hardware reset) and LED # 2 as output
PHY address Bit 0 as input (during power on reset and hardware reset) and LED #
0(function configurable, default is "activity/no activity") as output
PHY address Bit 1 as input (during power on reset and hardware reset) and LED #
1 (function configurable, default is "10/100 mode") as output
Output 25 MHz crystal output, floating if clock is used on REFIN
Notes:
1. AIO: Analog input/output PAD.
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.
3. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
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ICS1894-44
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10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
PHYCEIVER
Strapping Options
Pin
Number
16
17
18
38
19
12
40
39
21
20
22
Pin
Name
HWSW/CRS
REGPIN/COL
AMDIX/RXD2
P4/LED2
P3/RXD2
P2/INT
P1/ISO/LED1
P0/LED0
SI/LED4
RXTRI/RXD1
FDPX/RXD0
Pin
Type
1
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipu
IO/Ipd
IO/Ipd
IO/
IO/
IO/Ipd
IO/Ipd
IO/Ipu
Pin Function
Hardware pin select enable. Active during power-on and hardware reset.
Full register access enable. Active during power-on and hardware reset.
1 = AMDIX enable
0 = AMDIX disable
The PHY address is set by P[4:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
MII/SI mode select.
Active during power-on and hardware reset.
1=Realtime receiver isolation enable
2
;
0=RX output enable
1=Full duplex
0=Half duplex
Ignored if Auto negotiation is enabled
1=not supported
0=MII mode
1=100M mode
0=10M mode
1=Enable auto negotiation
0=Disable auto negotiation
0=Node mode
1=repeater mode
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
LED3 output
23
24
26
27
28
RXDV
SPEED
3
ANSEL/RXCLK
NOD/RXER
SPEED/TXCLK
3
IO/Ipd
IO/Ipu
IO/Ipu
IO/Ipd
IO/Ipu
32
LED3
IO/Ipu
1.
IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2.
If RXTRI/RXD1 pin is latched high during power on reset/hardware reset, P1/ISO/LED1 functions as RX real time
isolation control input after latch and LED1 function will be disabled.
3.
When Autonegotiation is enabled, the speed will be determined by the result of Autonegotiation between the link
partners. When Autonegotiation is not enabled, the speed will be determined by the state of either a real-time pin
(pin 24) or a register bit (00.13); whether pin 24 or Register 00.13 is in control in this case is determined by
register bit 19.14, which in turn has a latched-in default value from pin 16.
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE
5
ICS1894-44
REV B 030112
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