CMOS SuperSync FIFO
™
8,192 x 18
16,384 x 18
FEATURES
•
•
•
•
•
IDT72255LA
IDT72265LA
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Choose among the following memory organizations:
IDT72255LA
—
8,192 x 18
IDT72265LA
—
16,384 x 18
Pin-compatible with the IDT72275/72285 SuperSync FIFOs
10ns read/write cycle time (8ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First
Word Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls. These
FIFOs offer numerous improvements over previous SuperSync FIFOs,
including the following:
•
The limitation of the frequency of one clock input with respect to the other has
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
•
The period required by the retransmit operation is now fixed and short.
•
The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D
0
-D
17
L D SEN
INPUT REGISTER
OFFSET REGISTER
F F
/IR
PAF
EF
/OR
P AE
HF
FWFT/SI
WRITE CONTROL
LOGIC
RAM ARRAY
8,192 x 18
16,384 x 18
FLAG
LOGIC
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
OUTPUT REGISTER
MRS
P RS
RT
RESET
LOGIC
RCLK
REN
OE
Q
0
-Q
17
4670 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync FIFO is a trademark of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
JULY 2014
DSC-4670/4
©
2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
SuperSync FIFOs are particularly appropriate for networking, video,
telecommunications, data communications and other applications that need to
buffer large amounts of data.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN
is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (REN) input. Data is read from the FIFO on every rising edge
of RCLK when
REN
is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to f
MAX
with complete independence. There are no restrictions on the frequency
of one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In
IDT Standard mode,
the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
REN
and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
PIN CONFIGURATIONS
LD
FWFT/SI
GND
WCLK
PRS
EF/OR
RCLK
REN
RT
OE
MRS
FF/IR
PAF
HF
V
CC
PAE
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
WEN
SEN
DC
V
CC
GND
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q17
Q16
GND
Q15
Q14
V
CC
Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND
D5
D4
D3
D2
D1
D0
GND
Q0
Q1
GND
Q2
Q3
V
CC
Q4
Q5
D6
4670 drw02
TQFP (PN64, ORDER CODE: PF)
STQFP (PP64, ORDER CODE: TF)
TOP VIEW
NOTE:
1. DC = Don’t Care. Must be tied to GND or V
CC
, cannot be left open.
2
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
In
FWFT mode,
the first word written to an empty FIFO is clocked directly to
the data output lines after three transitions of the RCLK signal. A
REN
does not
have to be asserted for accessing the first word. However, subsequent words
written to the FIFO do require a LOW on
REN
for access. The state of the FWFT/
SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO can
provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR
(Empty Flag or Output Ready),
FF/
IR
(Full Flag or Input Ready),
HF
(Half-full Flag),
PAE
(Programmable Almost-
Empty flag) and
PAF
(Programmable Almost-Full flag). The
EF
and
FF
functions
are selected in IDT Standard mode. The
IR
and
OR
functions are selected in
FWFT mode.
HF, PAE
and
PAF
are always available for use, irrespective of
timing mode.
PAE
and
PAF
can be programmed independently to switch at any point in
memory. (See Table I and Table 2.) Programmable offsets determine the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, so that
PAE
can be set to switch at 127
or 1,023 locations from the empty boundary and the
PAF
threshold can be set
at 127 or 1,023 locations from the full boundary. These choices are made with
the
LD
pin during Master Reset.
For serial programming,
SEN
together with
LD
on each rising edge of WCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming,
WEN
together with
LD
on each rising edge of WCLK, are used
to load the offset registers via Dn.
REN
together with
LD
on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: The read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The
LD
pin selects either a partial flag default
setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag programming
method, and default or programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect.
PRS
is useful for resetting a device in mid-operation, when
reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the
RT
input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72255LA/72265LA are fabricated using IDT’s high speed submi-
cron CMOS technology.
PARTIAL RESET (PRS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA IN (
0
- D
n
)
D
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
DATA OUT (
0
- Q
n
)
Q
IDT
72255LA
72265LA
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF FULL FLAG (HF)
4670 drw03
Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO
3
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D
0
–D
17
MRS
Name
Data Inputs
Master Reset
I/O
I
I
Description
Data inputs for a 18-bit bus.
MRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program
mable flag default settings, and serial or parallel programming of the offset settings.
PRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During
Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and
programmable flag settings are all retained.
RT
asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the
EF
flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings.
RT
is useful to reread data from the first
physical location of the FIFO.
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
this pin functions as a serial input for loading offset registers.
When enabled by
WEN,
the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming, and when enabled by
SEN,
the rising edge of
WCLK writes one bit of data into the programmable register for serial programming.
WEN
enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by
REN,
the rising edge of RCLK reads data from the FIFO memory and offsets from
the programmable registers.
REN
enables RCLK for reading data from the FIFO memory and offset registers.
OE
controls the output impedance of Q
n.
SEN
enables serial loading of programmable flag offsets.
During Master Reset,
LD
selects one of two partial flag default offsets (127 or 1,023) and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
and reading from the offset registers.
This pin must be tied to either V
CC
or GND and must not toggle after Master Reset.
In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or not the FIFO
memory is full. In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not
there is space available for writing to the FIFO memory.
In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO
memory is empty. In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is
valid data available at the outputs.
PAF
goes LOW if the number of words in the FIFO memory is more than total word capacity of the
FIFO minus the full offset value m, which is stored in the Full Offset register. There are two possible
default values for m: 127 or 1,023.
PAE
goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in
the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values
for n can be programmed into the device.
HF
indicates whether the FIFO memory is more or less than half-full.
Data outputs for an 18-bit bus.
+5 Volt power supply pins.
Ground pins.
PRS
Partial Reset
I
RT
Retransmit
I
FWFT/SI
WCLK
First Word Fall
Through/Serial In
Write Clock
I
I
WEN
RCLK
REN
OE
SEN
LD
Write Enable
Read Clock
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
I
I
DC
FF/IR
Don't Care
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost-Full Flag
Programmable
Almost-Empty Flag
Half-Full Flag
Data Outputs
Power
Ground
I
O
EF/OR
O
PAF
O
PAE
O
HF
Q
0
–Q
17
V
CC
GND
O
O
4
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage
with respect to GND
Storage
Temperature
DC Output Current
Com’l & Ind’l
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
(1)
T
A
T
A
Parameter
Supply Voltage (Com’l/Ind’l)
Supply Voltage (Com’l/Ind’l)
Input High Voltage (Com’l/Ind’l)
Input Low Voltage (Com’l/Ind’l)
Operating Temperature
Commercial
Operating Temperature
Industrial
Min.
4.0
0
2.0
⎯
0
-40
Typ.
5.0
0
⎯
⎯
⎯
⎯
Max.
5.5
0
—
0.8
+70
+85
Unit
V
V
V
V
°C
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V
±
10%, T
A
= -40°C to +85°C)
IDT72255LA
IDT72265LA
Commercial & Industrial
(1)
t
CLK
= 10, 15, 20 ns
Symbol
I
LI
(2)
I
LO
(3)
V
OH
V
OL
I
CC1
(4,5,6)
I
CC2
(4,7)
Parameter
Input Leakage Current
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Standby Current
Min.
–1
–10
2.4
—
—
—
Max.
1
10
—
0.4
80
20
Unit
μA
μA
V
V
mA
mA
NOTES:
1. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.
2. Measurements with 0.4
≤
V
IN
≤
V
CC
.
3.
OE
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
4. Tested with outputs disabled (I
OUT
= 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical I
CC1
= 15 + 2.1*f
S
+ 0.02*C
L
*f
S
(in mA) with V
CC
= 5V, T
A
= 25°C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data
switching at f
S
/2, C
L
= capacitive load (in pF).
7. All Inputs = V
CC
–0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
NOTES:
1. With output deselected, (OE
≥
V
IH
).
2. Characterized values, not currently tested.
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
