IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 32-BIT
EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
μ
• Rail-to-Rail output swing for increased noise margin
• Available in 96-ball LFBGA package
IDT74ALVCH32374
DESCRIPTION:
This 32-bit edge-triggered D-type flip-flop is built using advanced dual
metal CMOS technology. This high-speed, low-power register is ideal for
use as a buffer register for data synchronization and storage. The Output
Enable (OE) and clock (CLK) controls are organized to operate the device
as four 8-bit registers, two 16-bit registers, or one 32-bit register with
common clock. Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise margin.
The ALVCH32374 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH32374 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistor.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for Heavy Loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
A3
3
OE
J3
A4
1
CLK
1
D
1
A5
3
CLK
J4
D
C
A2
3
D
1
1
Q
1
J5
D
C
J2
3
Q
1
TO SEVEN OTHER CHANNELS
H3
TO SEVEN OTHER CHANNELS
2
OE
4
OE
T3
H4
2
CLK
E5
4
CLK
T4
2
D
1
D
C
E2
4
D
1
2
Q
1
N5
D
C
N2
4
Q
1
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
©2009 Integrated Device Technology, Inc.
AUGUST 2009
DSC-4909/5
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
1
D
2
1
D
4
1
D
6
1
D
8
2
D
2
2
D
4
2
D
6
2
D
7
3
D
2
3
D
4
3
D
6
3
D
8
4
D
2
4
D
4
4
D
6
4
D
7
5
1
D
1
1
D
3
1
D
5
1
D
7
2
D
1
2
D
3
2
D
5
2
D
8
3
D
1
3
D
3
3
D
5
3
D
7
4
D
1
4
D
3
4
D
5
4
D
8
4 1
CLK
GND
GND
1
Q
3
V
CC
V
CC
1
Q
5
GND
GND
1
Q
7
GND
GND
2
Q
1
V
CC
V
CC
2
Q
3
GND
GND
2
Q
5
2
CLK
3
CLK
GND
GND
3
Q
3
V
CC
V
CC
3
Q
5
GND
GND
3
Q
7
GND
GND
4
Q
1
V
CC
V
CC
4
Q
3
GND
4
CLK
3 1
OE
2
OE
3
OE
GND
4
Q
5
4
OE
2
1
Q
1
2
Q
8
3
Q
1
4
Q
8
1
1
Q
2
A
1
Q
4
B
1
Q
6
C
1
Q
8
D
2
Q
2
E
2
Q
4
F
2
Q
6
G
2
Q
7
H
3
Q
2
J
3
Q
4
K
3
Q
6
L
3
Q
8
M
4
Q
2
N
4
Q
4
P
4
Q
6
R
4
Q
7
T
LFBGA
TOPVIEW
96 BALL LFBGA PACKAGE ATTRIBUTES
1.5mm Max.
1.4mm Nom.
1.3mm Min.
0.8mm
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TOP VIEW
A
1
2
3
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
5.5mm
4
5
6
13.5mm
2
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
Max
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
Unit
V
V
°C
mA
mA
mA
mA
V
TERM
(3)
Terminal Voltage with Respect to GND
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
PIN DESCRIPTION
Pin Names
xDx
xCLK
xQx
xOE
Data Inputs
(1)
Clock Inputs
3-State Outputs
3-State Output Enable Inputs (Active LOW)
Description
FUNCTION TABLE
(EACH FLIP-FLOP)
(1)
Inputs
xOE
L
L
L
H
xCLK
↑
↑
H or L
X
xDx
H
L
X
X
Outputs
xQx
H
L
Q
(2)
Z
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH Transition
2. Output level of Q before the indicated steady-state conditions were established.
3
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
Parameter
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
ΔI
CC
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
±500
Unit
µA
µA
µA
4
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
62
32
V
CC
= 3.3V ± 0.3V
Typical
60
36
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK(O)
Propagation Delay
xCLK to xQx
Output Enable Time
xOE
to xQx
Output Disable Time
xOE
to xQx
Setup Time, data before CLK↑
Hold Time, data after CLK↑
Pulse Duration, CLK HIGH or LOW
Output Skew
(2)
2.1
0.6
3.3
—
—
—
—
—
2.2
0.5
3.3
—
—
—
—
—
1.9
0.5
3.3
—
—
—
—
500
ns
ns
ns
ps
1
5.3
—
4.7
1.2
4.3
ns
1
6.2
—
5.9
1
4.8
ns
Parameter
Min.
150
1
Max.
—
5.3
V
CC
= 2.7V
Min.
150
—
Max.
—
4.9
V
CC
= 3.3V ± 0.3V
Min.
150
1
Max.
—
4.2
Unit
MHz
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
5
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