DATASHEET
3.3 VOLT COMMUNICATIONS CLOCK PLL
Description
The MK2049-36 is a Phased Locked Loop (PLL) based
clock synthesizer that accepts multiple input frequencies.
With an 8 kHz clock input as a reference, the MK2049-36
generates T1, E1, T3, E3, OC3 and other communications
frequencies. This allows for the generation of clocks
frequency-locked to an 8 kHz backplane clock, simplifying
clock synchronization in communications systems.
This part also has a jitter-attenuated Buffer capability. In this
mode, the MK2049-36 is ideal for filtering jitter from clocks
with high jitter.
IDT can customize these devices for many other different
frequencies. Contact your IDT representative for more
details.
MK2049-36
Features
•
•
•
•
Packaged in 20 pin SOIC
Pb (lead) free package
3.3 V + 5% operation
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
50 MHz
•
Accepts multiple inputs: 8 kHz backplane clock or 10 to
•
Locks to 8 kHz + 100 ppm (External mode)
•
Buffer Mode allows jitter attenuation of 10 - 50 MHz input
and x1/x0.5 or x1/x2 outputs
•
Exact internal ratios enable zero ppm error
•
Output clock rates include T1, E1, T3, E3, and OC3
submultiples
•
See also the MK2049-34 and MK2049-45
Block Diagram
E
XTERNAL
P
ULLABLE
C
RYSTAL
I
NPUT
R
EFERENCE
C
LOCK
(T
YPICALLY
8
K
H
Z
)
VCXO-B
ASED
PLL
(M
ASTER
C
LOCK
G
ENERATOR
)
F
REQUENCY
M
ULTIPLYING
PLL
2
C
LOCK
O
UTPUT
C
LOCK
O
UTPUT
/ 2
8
K
H
Z
(R
EGENERATED
)
F
REQUENCY
S
ELECT
4
IDT®
3.3 VOLT COMMUNICATIONS CLOCK PLL
1
MK2049-36
REV G 051310
MK2049-36
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Pin Assignment
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FS0
RES
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
20 pin (300) mil SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin
Name
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
Pin
Type
Input
XO
XI
Power
-
Power
Power
Output
Output
Output
Input
Input
Input
Power
Power
Loop
Filter
Power
Loop
Pin Description
Frequency select 1. Determines CLK input/outputs per table on page 3.
Internal pull-up resistor.
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
Power supply. Connect to +3.3 V.
Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
Power supply. Connect to +3.3 V.
Connect to ground
Clock output determined by status of FS3:0 per tables on page 3.
Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of
CLK.
Recovered 8 kHz clock output.
Frequency select 2. Determines CLK input/outputs per tables on page 3.
Internal pull-up resistor.
Frequency select 3. Determines CLK input/outputs per tables on page 3.
Internal pull-up resistor.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Power Supply. Connect to +3.3 V.
Connect the loop filter ceramic capacitors and resistor between this pin and
CAP2.
Connect to ground.
Connect the loop filter ceramic capacitors and resistor between this pin and
IDT®
3.3 VOLT COMMUNICATIONS CLOCK PLL
2
MK2049-36
REV G 051310
MK2049-36
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Pin
Number
19
20
Pin
Name
RES
FS0
Pin
Type
-
Input
Pin Description
Connect a 10-200kΩ resistor to ground. Contact IDTfor recommended value
for your application.
Frequency select 0. Determines CLK input/outputs per table on page 3.
Internal pull-up resistor.
Output Decoding Table - External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK/2
1.544
2.048
22.368
17.184
77.76
16.384
14.352
TEST
18.528
12.352
7.68
TEST
12.288
16.384
CLK
3.088
4.096
44.736
34.368
155.52
32.768
28.704
TEST
37.056
24.704
15.36
TEST
24.576
32.768
8k
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
TEST
8 kHz
8 kHz
8 kHz
TEST
8 kHz
8 kHz
Crystal
Used (MHz)
12.352
12.288
11.184
11.456
19.44
16.384
14.352
TEST
18.528
24.704
15.36
TEST
24.576
12.288
N
1544
1536
1398
1432
2430
2048
1794
TEST
2316
3088
1920
1344
3072
1536
Output Decoding Table - Buffer Mode (MHz)
ICLK
22 - 36
11 - 18
FS3
1
1
FS2
1
1
FS1
1
1
FS0
0
1
CLK/2
ICLK/2
2*ICLK
CLK
ICLK
4*ICLK
8k
N/A
N/A
Crystal
ICLK/2
ICLK
N
3
3
0 = connect directly to ground, 1 = connect directly to VDD or leave open.
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
Operating Modes
The MK2049-36 has two operating modes: External and Buffer. Although both modes use an input clock to generate various
output clocks, there are important differences in their input and crystal requirements.
External Mode
The MK2049-36 accepts an external 8 kHz clock and will produce a number of common communication clock frequencies.
The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10 ns is acceptable.
Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a wider range of
input clocks. The input jitter is attenuated and the outputs on CLK and CLK/2 also provide the option of getting x1, x2, x4, or
1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz clock, generating
low-jitter 27 MHz and 13.5 MHz outputs.
IDT®
3.3 VOLT COMMUNICATIONS CLOCK PLL
3
MK2049-36
REV G 051310
MK2049-36
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Frequency Locking to the Input
In all modes, the output clocks are frequency-locked to the input. The outputs will remain at the specified output frequency
as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For example, if the
crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by up to 60 ppm and
still have the output clock remain frequency-locked.
PC Board Layout
A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins are very
sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and the two
capacitors and resistor must be mounted next to the device as shown below. The capacitor shown between pins 15 and 17,
and the one between pins 4 and 7 are the power supply decoupling capacitors. The high frequency output clocks on pins 8
and 9 should have a series termination of 33Ω connected close to the pin. Additional improvements will come from keeping
all components on the same side of the board, minimizing vias through other signal layers, and routing other signals away
from the MK2049. You may also refer to application note MAN05 for additional suggestions on layout of the crystal selection.
The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the stray
capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is accurate to
much less than 1 ppm, so the MK2049 may lock and run properly even if the board capacitance is not adjusted with these
fixed capacitors. However, IDT recommends that the adjustment capacitors be included to minimize the effects of variation
in individual crystals, temperature, and aging. The value of these capacitors (typically 0 - 4 pF) is determined once for a
given board layout, using the procedure found in application note MAN05 on the IDT web site.
Cutout in ground and power plane.
Route all traces away from this area.
Optional -
see text
cap
G
cap
1
2
3
4
5
cap
cap
20
19
18
17
16
15
14
13
12
11
G
cap
resist
G
resist
cap
V
cap
resist
resist
6
7
8
9
10
V
V
G
= connect to VDD
= connect to GND
Figure 2. Typical MK2049-34 Layout
External Component Selection
The MK2049-36 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01μF
must be connected between VDD and GND pins close to the chip (especially pins 4 and 7, 15 and 17), and 33Ω series
terminating resistors should be used on clock outputs with traces longer than one inch (assuming 50Ω traces). The selection
of additional external components is described in the following sections.
IDT®
3.3 VOLT COMMUNICATIONS CLOCK PLL
4
MK2049-36
REV G 051310
MK2049-36
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Loop Filter
Information on how to configure the external loop filter (connected between pins CAP1 and CAP2) can be found on our web
site at www.idt.com/?app=calculators&source=support_menu.
Crystal Operation
The MK2049-36 operates by phase locking the input signal to a VCXO which consists of the recommended pullable VCXO
crystals and the integrated VCXO oscillator circuit on the MK2049. To achieve the best performance and reliability, the
layout guidelines shown on the previous page should be closely followed.
The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The
MK2049 has variable load capacitors on-chip which “pull” or change the frequency of the crystal. External stray capacitance
must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the layout should use short traces
between the MK2049 and the crystal.
For the VCXO to operate correctly, a pullable crystal must be used. For more information, including a list of approved
crystals, please refer to application note MAN05 on the IDT web site.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2049-36. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
175° C
250° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.15
Typ.
+3.3
Max.
+85
+3.45
Units
°
C
V
IDT®
3.3 VOLT COMMUNICATIONS CLOCK PLL
5
MK2049-36
REV G 051310
嵌入式系统
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