CY7C106D
CY7C1006D
1-Mbit (256 K × 4) Static RAM
1-Mbit (256 K × 4) Static RAM
Features
■
■
Functional Description
The CY7C106D
[1]
and CY7C1006D
[1]
are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE), an active LOW Output Enable (OE), and tri-state drivers.
These devices have an automatic power-down feature that
reduces power consumption by more than 65% when the
devices are deselected. The four input and output pins (IO
0
through IO
3
) are placed in a high-impedance state when:
■
■
■
Pin- and function-compatible with CY7C106B/CY7C1006B
High speed
❐
t
AA
= 10 ns
Low active power
❐
I
CC
= 80 mA @ 10 ns
Low CMOS standby power
❐
I
SB2
= 3.0 mA
2.0 V Data Retention
Automatic power-down when deselected
CMOS for optimum speed/power
TTL-compatible inputs and outputs
CY7C106D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1006D available in Pb-free 28-pin 300-Mil
wide Molded SOJ package
■
■
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
When the write operation is active (CE and WE LOW)
■
■
■
■
■
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the four IO pins (IO
0
through IO
3
) is
then written into the location specified on the address pins (A
0
through A
17
).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appears on the four IO pins.
Both CY7C106D and CY7C1006D devices are suitable for
interfacing with processors that have TTL I/P levels. They are not
suitable for processors that require CMOS I/P levels. Please see
Electrical Characteristics on page 4
for more details and
suggested alternatives.
For a complete list of related documentation,
click here.
Logic Block Diagram
INPUT BUFFER
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE
WE
OE
ROW DECODER
256K x 4
ARRAY
SENSE AMPS
IO0
IO1
IO2
IO3
COLUMN DECODER
POWER
DOWN
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
www.cypress.com.
A0
A10
A11
A12
A13
A14
A15
A16
A17
Cypress Semiconductor Corporation
Document Number: 38-05459 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 26, 2014
CY7C106D
CY7C1006D
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions and Legal Information ....................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Document Number: 38-05459 Rev. *K
Page 2 of 16
CY7C106D
CY7C1006D
Pin Configurations
Figure 1. 28-pin SOJ pinout (Top View)
[2]
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
CE
OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
NC
IO
3
IO
2
IO
1
IO
0
WE
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
CY7C106D-10
CY7C1006D-10
10
80
3
Unit
ns
mA
mA
Note
2. NC pins are not connected on the die.
Document Number: 38-05459 Rev. *K
Page 3 of 16
CY7C106D
CY7C1006D
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on
V
CC
Relative to GND
[3]
...............................–0.5 V to +6.0 V
DC Voltage Applied to Outputs
in High Z State
[3]
................................ –0.5 V to V
CC
+ 0.5 V
DC Input Voltage
[3]
............................ –0.5 V to V
CC
+ 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Range
Industrial
Ambient
Temperature
–40 °C to +85 °C
V
CC
5 V
0.5 V
Speed
10 ns
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current
GND < V
I
< V
CC
GND < V
I
< V
CC
, Output Disabled
V
CC
= Max, I
OUT
= 0 mA,
f = f
max
= 1/t
RC
100 MHz
83 MHz
66 MHz
40 MHz
I
SB1
I
SB2
Automatic CE Power-Down
Current — TTL Inputs
Automatic CE Power-Down
Current — CMOS Inputs
Max V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
max
Max V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V or V
IN
< 0.3 V, f = 0
I
OH
= –4.0 mA
I
OH
= –0.1 mA
I
OL
= 8.0 mA
Test Conditions
7C106D-10
7C1006D-10
Min
2.4
–
–
2.2
–0.5
–1
–1
–
–
–
–
–
–
Max
–
3.4
[4]
0.4
V
CC
+ 0.5
0.8
+1
+1
80
72
58
37
10
3
V
V
V
A
A
mA
mA
mA
mA
mA
mA
V
Unit
Note
3. V
IL
(min) = –2.0 V and V
IH
(max) = V
CC
+ 1 V for pulse durations of less than 5 ns.
4. Please note that the maximum V
OH
limit does not exceed minimum CMOS V
IH
of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
minimum V
IH
of 3.5 V, please refer to Application Note
AN6081
for technical details and options you may consider.
Document Number: 38-05459 Rev. *K
Page 4 of 16
CY7C106D
CY7C1006D
Capacitance
Parameter
C
IN
: Controls
C
OUT
Output capacitance
[5]
Description
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= 5.0 V
Max
7
10
10
Unit
pF
pF
pF
C
IN
: Addresses Input capacitance
Thermal Resistance
Parameter
JA
JC
[5]
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
300-Mil Wide
SOJ
59.16
40.84
400-Mil Wide
SOJ
58.76
40.54
Unit
°C/W
°C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
[6]
Z = 50
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5 V
3.0 V
ALL INPUT PULSES
90%
10%
90%
10%
30 pF*
GND
Rise Time:
3
ns
(a)
(b)
Fall Time:
3
ns
High Z characteristics:
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
R2
255
R1 480
(c)
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High Z) are tested using the load conditions shown in part (a) of
Figure 2.
High Z characteristics are tested for all speeds using the test
load shown in part (c) of
Figure 2.
Document Number: 38-05459 Rev. *K
Page 5 of 16
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
