PRELIMINARY
Programmable System-on-Chip (PSoC )
General Description
PSoC
®
Analog Coprocessor:
CY8C4Axx Family Datasheet
®
Cypress's PSoC
®
Analog Coprocessor is a scalable and reconfigurable platform architecture of programmable analog coprocessors
that simplify designing embedded systems with multiple sensors. The PSoC Analog Coprocessor device combines PSoC's flexible
Analog Front Ends, programmable analog filters, and high-resolution analog-to-digital converters along with an efficient yet powerful
32-bit ARM
®
Cortex
®
-M0+ based signal processing engine – enabling host processors to easily fetch aggregated, pre-processed,
and formatted complex sensor data over serial communication interfaces.
Features
Programmable Analog Blocks
■
32-bit Signal Processing Engine
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A switched-capacitor Universal Analog Block (UAB) program-
mable via PSoC Creator as a second-order analog filter, a
14-bit Incremental Delta-Sigma ADC, or a 13-bit Voltage DAC
Two dedicated analog-to-digital converters (ADC) including a
12-bit SAR ADC and a 10-bit single-slope ADC
Four opamps, two low-power comparators, and a flexible
38-channel analog mux to create custom Analog Front Ends
(AFE)
Two 7-bit Current DACs (IDACs) for general-purpose or capac-
itive sensing applications on any pin
ARM Cortex-M0+ CPU up to 48 MHz
Up to 32 KB of flash with read accelerator
Up to 4 KB of SRAM
Eight-channel descriptor-based DMA controller
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■
Low-Power Operation
■
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1.71-V to 5.5-V operation
Deep-Sleep mode with operational analog and 2.5-µA digital
system current
Watch Crystal Oscillator (WCO)
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CapSense
®
Capacitive Sensing
■
Cypress's fourth-generation CapSense Sigma-Delta (CSD)
providing best-in-class signal-to-noise ratio (SNR) and water
tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning (SmartSense™)
Programmable GPIO Pins
■
■
■
Up to 38 GPIOs that can be used for analog, digital, CapSense,
or LCD functions with programmable drive modes, strength and
slew rates
Includes eight Smart I/Os to implement pin-level Boolean
operations on input and output signals
48-pin QFN, 48-pin TQFP, 28-pin SSOP, and 45-ball WLCSP
packages
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■
Segment LCD Drive
■
■
LCD drive supported on all pins (common or segment)
Operates in Deep-Sleep mode with four bits per pin memory
■
PSoC Creator Design Environment
Integrated Design Environment (IDE) provides
schematic-capture design entry and build (with automatic
routing of analog and digital signals) and concurrent firmware
development with an ARM-SWD debugger
GUI-based configurable PSoC Components with fully
engineered embedded initialization, calibration and correction
algorithms
Application Programming Interfaces (API) for all fixed-function
and programmable peripherals
Programmable Digital Peripherals
■
■
Three independent serial communication blocks (SCBs) that
are run-time configurable as I2C, SPI or UART
Eight 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks with center-aligned, edge, and pseudo-random modes
■
■
Industry-Standard Tool Compatibility
■
After schematic-capture, firmware development can be done
with ARM-based industry-standard development tools
Cypress Semiconductor Corporation
Document Number: 001-96467 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 11, 2016
PRELIMINARY
PSoC
®
Analog Coprocessor:
CY8C4Axx Family Datasheet
Contents
Functional Definition........................................................ 4
CPU and Memory Subsystem ..................................... 4
System Resources ...................................................... 4
Analog Blocks.............................................................. 5
Fixed Function Digital.................................................. 6
GPIO ........................................................................... 6
Special Function Peripherals....................................... 7
WLCSP Package Bootloader ...................................... 7
Pinouts .............................................................................. 8
Alternate Pin Functions ............................................. 10
Power............................................................................... 12
Mode 1: 1.8 V to 5.5 V External Supply .................... 12
Development Support .................................................... 13
Documentation .......................................................... 13
Online ........................................................................ 13
Tools.......................................................................... 13
Electrical Specifications ................................................ 14
Absolute Maximum Ratings....................................... 14
Device Level Specifications....................................... 14
Analog Peripherals .................................................... 18
Digital Peripherals ..................................................... 28
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Packaging........................................................................
Package Diagrams ....................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Errata ...............................................................................
Part Numbers Affected ..............................................
PSoC Analog Coprocessor Qualification Status .......
PSoC Analog Coprocessor Errata Summary ............
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
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30
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Document Number: 001-96467 Rev. *F
Page 2 of 43
PRELIMINARY
PSoC
®
Analog Coprocessor:
CY8C4Axx Family Datasheet
Figure 1. Block Diagram
PSoC Analog Coprocessor
Architecture
32-bit
CPU Subsystem
SWD/TC
SPCIF
Cortex
M0+
48 MHz
FAST MUL
NVIC, IRQMX
FLASH
32 KB
Read Accelerator
SRAM
4 KB
SRAM Controller
ROM
8 KB
ROM Controller
DataWire/
DMA
Initiator / MMIO
AHB- Lite
System Resources
Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
IMO
ILO
System Interconnect (Multi Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
Programmable
Analog
3x SCB-
I2C/SPI/UART
IOSS GPIO
(6x ports)
UAB
Test
DFT Logic
DFT Analog
x1
x1
SMX
CTB
x2
2x OpAmp
Power Modes
Active / Sleep
Deep Sleep
High Speed I/ O Matrix, 1 x PRGIO
38 x GPIO, LCD
I/O Subsystem
PSoC Analog Coprocessor devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC Analog Coprocessor devices.
The SWD interface is fully compatible with industry-standard
third-party tools. The PSoC Analog Coprocessor family provides
a level of security not possible with multi-chip application
solutions or with microcontrollers. It has the following
advantages:
■
■
■
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC Analog Coprocessor, with device security enabled, may
not be returned for failure analysis. This is a trade-off the PSoC
Analog Coprocessor allows the customer to make.
Allows disabling of debug features
Robust flash protection
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 001-96467 Rev. *F
WCO
Reset
Reset Control
XRES
SAR
ADC
(12-bit)
2x LP Comparator
8x TCPWM
CapSense
Page 3 of 43
PRELIMINARY
PSoC
®
Analog Coprocessor:
CY8C4Axx Family Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in the PSoC Analog Coprocessor is part
of the 32-bit MCU subsystem, which is optimized for low-power
operation with extensive clock gating. Most instructions are 16
bits in length and the CPU executes a subset of the Thumb-2
instruction set. It includes a nested vectored interrupt controller
(NVIC) block with eight interrupt inputs and also includes a
Wakeup Interrupt Controller (WIC). The WIC can wake the
processor from Deep Sleep mode, allowing power to be switched
off to the main processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug
configuration used for PSoC Analog Coprocessor has four
breakpoint (address) comparators and two watchpoint (data)
comparators.
DMA/DataWire
The DMA engine will be capable of doing independent data
transfers anywhere within the memory map via a user-program-
mable descriptor chain. The DataWire capability is used to effect
single-element transfers from one location in memory to another.
There are eight DMA channels with a range of selectable trigger
sources.
Flash
The PSoC Analog Coprocessor device has a flash module with
a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash
block is designed to deliver two wait-state (WS) access time at
48 MHz. The flash accelerator delivers 85% of single-cycle
SRAM access performance on average.
SRAM
Four KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
Eight KB of SROM are provided that contain boot and configu-
ration routines.
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Clock System
The PSoC Analog Coprocessor clock system is responsible for
providing clocks to all subsystems that require clocks and for
switching between different clock sources without glitching. In
addition, the clock system ensures that there are no metastable
conditions.
The clock system for the PSoC Analog Coprocessor consists of
the internal main oscillator (IMO), internal low-frequency oscil-
lator (ILO), a 32 kHz Watch Crystal Oscillator (WCO) and
provision for an external clock. Clock dividers are provided to
generate clocks for peripherals on a fine-grained basis.
Fractional dividers are also provided to enable clocking of higher
data rates for UARTs.
Figure 2. PSoC Analog Coprocessor MCU Clocking Archi-
tecture
IMO
Divide By
2,4,8
HFCLK
External Clock
ILO
LFCLK
HFCLK
Prescaler
Integer
Dividers
Fractional
Dividers
SYSCLK
10X 16-bit
4X 16.5-bit, 1X 24.5-bit
System Resources
Power System
The power system is described in detail in the section
Power on
page 12.
It provides an assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC Analog Copro-
cessor operates with a single external supply over the range of
either 1.8 V ±5% (externally regulated) or 1.8 to 5.5 V (internally
regulated) and has three different power modes, transitions
between which are managed by the power system. The PSoC
Analog Coprocessor provides Active, Sleep, and Deep Sleep
low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
Document Number: 001-96467 Rev. *F
The HFCLK signal can be divided down to generate
synchronous clocks for the analog and digital peripherals. There
are 15 clock dividers for the PSoC Analog Coprocessor. The
16-bit capability allows flexible generation of fine-grained
frequency values (there is one 24-bit divider for large divide
ratios), and is fully supported in PSoC Creator.
IMO Clock Source
The IMO is the primary source of internal clocking in the PSoC
Analog Coprocessor. It is trimmed during testing to achieve the
specified accuracy.The IMO default frequency is 24 MHz and it
can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO
tolerance with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Page 4 of 43
PRELIMINARY
PSoC
®
Analog Coprocessor:
CY8C4Axx Family Datasheet
Watch Crystal Oscillator (WCO)
The PSoC Analog Coprocessor clock subsystem also imple-
ments a low-frequency (32-kHz watch crystal) oscillator that can
be used for precision timing applications.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
Reset
The PSoC Analog Coprocessor can be reset from a variety of
sources including a software reset. Reset events are
asynchronous and guarantee reversion to a known state. The
reset cause is recorded in a register, which is sticky through reset
and allows software to determine the cause of the reset. An
XRES pin is reserved for external reset by asserting it active low.
The XRES pin has an internal pull-up resistor that is always
enabled.
Voltage Reference
The PSoC Analog Coprocessor reference system generates all
internally required references. A 1.2-V voltage reference is
provided for the comparator. The IDACs are based on a ±5%
reference.
Analog Blocks
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The Sample-and-Hold (S/H) aperture is programmable allowing
the gain bandwidth requirements of the amplifier driving the SAR
inputs, which determine its settling time, to be relaxed if required.
It is possible to provide an external bypass (through a fixed pin
location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) with zero switching overhead
(that is, aggregate sampling bandwidth is equal to 1 Msps
whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state
machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is
1.71 V to 5.5 V.
Figure 3. SAR ADC
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
Sequencing
and Control
vminus vplus
POS
Data and
Status Flags
P0
SARADC
NEG
SARMUX Port
(8 inputs)
SARMUX
P7
Reference
Selection
VDDA/2
VDDA
VREF
External
Reference
and
Bypass
(optional )
Inputs from other Ports
Four Opamps (Continuous-Time Block; CTB)
The PSoC Analog Coprocessor has four opamps with
Comparator modes which allow most common analog functions
to be performed on-chip eliminating external components;
PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers, and
other functions can be realized, in some cases with external
passives, saving power, cost, and space. The on-chip opamps
are designed with enough bandwidth to drive the
Sample-and-Hold circuit of the ADC without requiring external
buffering.
Universal Analog Block (UAB) Discrete-Time Block
The UAB Block consists of switched-capacitor feedback and
input networks connected to two opamp structures; the two
halves of the structure can be used independently, thus a bi-quad
filter structure can be made using the two halves independently
in single-ended mode. General analog functions can be
implemented with the switched-capacitor network and the
opamps examples of functions implementable with the UAB are:
DAC, multi-pole SC filters (cascadable blocks), delta-sigma
modulator, mixers, integrators, PGAs, and other useful functions
using Cypress PSoC Creator with Cypress-supplied software
components.
Page 5 of 43
Document Number: 001-96467 Rev. *F
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