Datasheet> 器件分类 > 半导体> 模拟混合信号IC> 82P33741BAG

82P33741BAG: 产品类别半导体模拟混合信号IC; 文件大小186KB，共12页; 制造商IDT(艾迪悌); 官网地址http://www.idt.com/

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82P33741BAG规格参数

参数名称	属性值
产品种类 Product Category	Clock Synthesizer / Jitter Cleaner
制造商 Manufacturer	IDT(艾迪悌)
RoHS	Details
系列 Packaging	Tray
工厂包装数量 Factory Pack Quantity	168

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Port Synchronizer for IEEE 1588 and 10G/

40G Synchronous Ethernet

82P33741

SHORT FORM DATA SHEET

HIGHLIGHTS

•

DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on

OUT8 and OUT9

APLL1, APLL2 and APLL3 can be connected to DPLL1 and DPLL2

APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or

SONET/SDH frequencies

APLL3 generates 10G Ethernet, WAN-PHY and LAN-PHY frequen-

cies

Any of eight common TCXO/OCXO frequencies can be used for the

System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,

24.576 MHz, 25 MHz or 30.72 MHz

The I2C slave interface can be used by a host processor to access

the control and status registers

The I2C master interface can automatically load a device configura-

tion from an external EEPROM after reset; APLL3 must be config-

ured via the I2C slave interface

Differential outputs OUT3 to OUT6 output clocks with frequencies

between 1 PPS and 650 MHz

Differential outputs OUT10 and OUT11 output clocks with frequen-

cies up to 650 MHz

Single ended outputs OUT1, OUT2, and OUT7 output clocks with fre-

quencies between 1 PPS and 125 MHz

Single ended outputs OUT8 and OUT9 output clocks N*8kHz multi-

ples up to 100 MHz

DPLL1 and DPLL2 support independent programmable delays for

each of IN1 to IN12; the delay for each input is programmable in

steps of 0.61 ns with a range of ~±78 ns

The input to output phase delay of DPLL1 and DPLL2 is programma-

ble in steps of 0.0745 ps with a total range of ±20

μs

The clock phase of each of the output dividers for OUT1 to OUT7 is

individually programmable in steps of ~200 ps with a total range of +/

-180°

1149.1 JTAG Boundary Scan

144-pin CABGA green package

Synchronous clock generation for 10/40G and lower rate, Ethernet,

PON OLT and SONET/SDH line card

Access routers, edge routers, core routers

Carrier Ethernet switches

Multiservice access platforms

PON OLT

LTE eNodeB

DPLL1 and DPLL2 can be used on line cards to manage the genera-

tion of synchronous port clocks and IEEE 1588 synchronization sig-

nals based on multiple system backplane references

DPLL3 can be used on line cards to select incoming line clocks for

use on system backplanes; it can also be used for general purpose

timing applications

APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to

20 MHz) for: 1000BASE-T and 1000BASE-X ports and to generate

IEEE 1588 time stamp clocks and 1 pulse per second (PPS) signals

APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and

generates clocks with jitter <0.3 ps RMS (10 kHz to 20 MHz) for:

10GBASE-R, 10GBASE-W and 40GBASE-R

Fractional-N input dividers support a wide range of reference fre-

quencies

DPLLs, APLL1 and APLL2 can be configured from an external

EEPROM after reset

Differential reference inputs (IN1 to IN6) accept clock frequencies

between 2 kHz and 650 MHz

Single ended inputs (IN7 to IN12) accept reference clock frequencies

between 2 kHz and 162.5 MHz

Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any

clock reference input

Reference monitors qualify/disqualify references depending on activ-

ity, frequency and LOS pins

Automatic reference selection state machines select the active refer-

ence for each DPLL based on the reference monitors, priority tables,

revertive and non-revertive settings and other programmable settings

Fractional-N input dividers enable the DPLLs to lock to a wide range

of reference clock frequencies including: 10/100/1000 Ethernet, 10G

Ethernet, OTN, SONET/SDH, PDH, TDM, GSM and GNSS frequen-

cies

Any reference inputs (IN1 to IN12) can be designated as external

sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a

selectable reference clock input

FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses

that are aligned with the selected external input sync pulse input and

frequency locked to the associated reference clock input

DPLL1 and DPLL2 can be configured with bandwidths between 18

Hz and 567 Hz

DPLL1 and DPLL2 lock to input references with frequencies between

2 kHz and 650 MHz

DPLL3 locks to input references with frequencies between 8 kHz and

650 MHz

DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/

OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks

are directly available on OUT1

FEATURES

•

APPLICATIONS

82P33741 REVISION 1 09/23/14

82P33741 SHORT FORM DATA SHEET

DESCRIPTION

The 82P33741 Port Synchronizer for IEEE 1588 and 10G/40G Synchronous Ethernet provides tools to manage timing references, clock conver-

sion and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588

clock generation; SyncE clock generation; and general purpose frequency translation. The device outputs low-jitter clocks that can directly synchro-

nize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and

IEEE 1588 Time Stamp Units (TSUs).

The 82P33741 accepts six differential reference inputs and six single ended reference inputs that can operate at common Ethernet, SONET/SDH

and PDH frequencies that range from 2 kHz to 650 MHz. The references are continually monitored for loss of signal and for frequency offset per user

programmed thresholds. All of the references are available to all three Digital PLLs (DPLLs). The active reference for each DPLL is determined by

forced selection or by automatic selection based on user programmed priorities, locking allowances, reference monitors, and LOS inputs.

The 82P33741 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1/DPLL2 can lock to the clock reference

and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference

inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals

can have a frequency of 1 PPS, 2 kHz, 4kHz or 8 kHz. This feature enables DPLL1/DPLL2 to phase align its frame sync and multi-frame sync outputs

with a sync input without the need use a low bandwidth setting to lock directly to the sync input.

The DPLLs support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode the DPLLs synthesize clocks based on

the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output fre-

quency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data

acquired while in Locked mode to generate accurate frequencies when input references are not available.

The 82P33741 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter-

mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the

DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked mode.

DPLL1 and DPLL2 can be configured with a range of selectable filtering bandwidths from 18 Hz to 567 Hz. DPLL3 is a wideband (BW > 25Hz) fre-

quency translator that can be used, for example, to convert a recovered SyncE clock to a 25MHz backplane clock.

Clocks generated by DPLL1 and DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The

output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces, and for IEEE 1588 time stamps clocks and 1 PPS

signals.

Clocks generated by DPLL1 and DPLL2 can be passed through APLL3 which is a voltage controlled crystal oscillator (VCXO) based jitter attenu-

ating APLL. APLL3 can be provisioned with one or two selectable crystal resonators to support up to two base frequencies. The output clocks gener-

ated by APLL3 are suitable for serial 10 GbE and lower rate interfaces.

All 82P33741 control and status registers are accessed through an I2C slave microprocessor interface. For configuring the DPLLs, APLL1 and

APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset. APLL3 must be configured via the I2C

slave interface.

PORT SYNCHRONIZER FOR IEEE 1588 AND

10G/40G SYNCHRONOUS ETHERNET

REVISION 1 09/23/14

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器件捷径: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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