INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT112
Dual JK flip-flop with set and reset;
negative-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jun 10
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
FEATURES
•
Asynchronous set and reset
•
Output capability: standard
•
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (nCP),
set (nS
D
) and reset (nR
D
) inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT112
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
A HIGH level at the clock (nCP) input enables the nJ and
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
17
15
18
66
3.5
27
19
15
19
70
3.5
30
ns
ns
ns
MHz
pF
pF
HCT
UNIT
1998 Jun 10
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
ORDERING INFORMATION
TYPE
NUMBER
74HC112D;
74HCT112D
74HC112DB;
74HCT112DB
74HC112N;
74HCT112N
74HC112PW;
74HCT112PW
PACKAGE
NAME
SO16
SSOP16
DIP16
TSSOP16
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm
74HC/HCT112
VERSION
SOT109-1
SOT338-1
SOT38-1
SOT403-1
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic dual in-line package; 16 leads (300 mil); long body
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION
PIN NO.
1, 13
2, 12
3, 11
4, 10
5, 9
6, 7
8
15, 14
16
SYMBOL
1CP, 2CP
1K, 2K
1J, 2J
1S
D
, 2S
D
1Q, 2Q
1Q, 2Q
GND
1R
D
, 2R
D
V
CC
NAME AND FUNCTION
clock input (HIGH-to-LOW, edge triggered)
data inputs; flip-flops 1 and 2
data inputs; flip-flops 1 and 2
set inputs (active LOW)
true flip-flop outputs
complement flip-flop outputs
ground (0 V)
reset inputs (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jun 10
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
FUNCTION TABLE
INPUTS
OPERATING MODE
nS
D
asynchronous set
asynchronous reset
undetermined
toggle
load “0” (reset)
load “1” (set)
hold “no change”
Note
L
H
L
H
H
H
H
nR
D
H
L
L
H
H
H
H
nCP
X
X
X
↓
↓
↓
↓
nJ
X
X
X
h
l
h
l
74HC/HCT112
OUTPUTS
nK
X
X
X
h
h
l
l
nQ
H
L
H
q
L
H
q
nQ
L
H
L
q
H
L
q
Fig.4 Functional diagram.
1. If nS
D
and nR
D
simultaneously go from LOW to HIGH, the output states will
be unpredictable.
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP
transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP
transition
q = lower case letters indicate the state of the referenced output one set-up
time prior to the HIGH-to-LOW CP transition
X = don’t care
↓
= HIGH-to-LOW CP transition
Fig.5 Logic diagram (one flip-flop).
1998 Jun 10
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: flip-flops
74HC/HCT112
1998 Jun 10
5
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