Logic-Level Gate Drive
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Advanced Process Technology
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Surface Mount (IRL2505S)
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Low-profile through-hole (IRL2505L)
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175°C Operating Temperature
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Fast Switching
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Fully Avalanche Rated
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Lead-Free
Description
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HEXFET Power MOSFET
D
IRL2505LPbF
IRL2505SPbF
®
V
DSS
= 55V
R
DS(on)
= 0.008Ω
PD - 95577
G
I
D
= 104A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL2505L) is available for low-
profile applications.
D 2 Pak
TO-262
Absolute Maximum Ratings
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
A
= 25°C
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
104
74
360
3.8
200
1.3
±16
500
54
20
5.0
-55 to + 175
300 (1.6mm from case )
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
Max.
0.75
40
Units
°C/W
07/19/04
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1
IRL2505S/LPbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
V
(BR)DSS
Drain-to-Source Breakdown Voltage
∆V
(BR)DSS
/∆T
J
Breakdown Voltage Temp. Coefficient
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min.
55
1.0
59
Typ. Max. Units
Conditions
V
V
GS
= 0V, I
D
= 250µA
0.035 V/°C Reference to 25°C, I
D
= 1mA
0.008
V
GS
= 10V, I
D
= 54A
0.010
Ω
V
GS
= 5.0V, I
D
= 54A
0.013
V
GS
= 4.0V, I
D
= 45A
2.0
V
V
DS
= V
GS
, I
D
= 250µA
S
V
DS
= 25V, I
D
= 54A
25
V
DS
= 55V, V
GS
= 0V
µA
250
V
DS
= 44V, V
GS
= 0V, T
J
= 150°C
100
V
GS
= 16V
nA
-100
V
GS
= -16V
130
I
D
= 54A
25
nC
V
DS
= 44V
67
V
GS
= 5.0V, See Fig. 6 and 13
12
V
DD
= 28V
160
I
D
= 54A
ns
43
R
G
= 1.3Ω, V
GS
= 5.0V
84
R
D
= 0.50Ω, See Fig. 10
Between lead,
7.5
nH
and center of die contact
5000
V
GS
= 0V
1100
pF
V
DS
= 25V
390
= 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
104
showing the
A
G
integral reverse
360
S
p-n junction diode.
1.3
V
T
J
= 25°C, I
S
= 54A, V
GS
= 0V
140 210
ns
T
J
= 25°C, I
F
= 54A
650 970
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
V
DD
= 25V, starting T
J
= 25°C, L = 240µH
R
G
= 25Ω, I
AS
= 54A. (See Figure 12)
I
SD
≤
54A, di/dt
≤
230A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C
Pulse width
≤
300µs; duty cycle
≤
2%.
Uses IRL2505 data and test conditions
Caculated continuous current based on maximum allowable
junction temperature;for recommended current-handling of the
package refer to Design Tip # 93-4
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRL2505S/LPbF
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
1000
I
D
, Drain-to-Source Current (A)
100
I
D
, Drain-to-Source Current (A)
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
100
2.5V
10
10
2.5V
20µs PULSE WIDTH
T
J
= 25°C
1
10
1
0.1
A
100
1
0.1
20µs PULSE WIDTH
T
J
= 175°C
1
10
A
100
V
DS
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
3.0
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
I
D
= 90A
I
D
, Drain-to-Source Current (A)
T
J
= 25°C
100
2.5
T
J
= 175°C
2.0
1.5
10
1.0
0.5
1
2.5
3.5
4.5
V
DS
= 25V
20µs PULSE WIDTH
5.5
6.5
7.5
A
0.0
-60 -40 -20
0
20
40
60
V
GS
= 10V
80 100 120 140 160 180
A
V
GS
, Gate-to-Source Voltage (V)
T
J
, Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
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3
IRL2505S/LPbF
10000
8000
V
GS
, Gate-to-Source Voltage (V)
V
GS
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd
, C
ds
SHORTED
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
15
I
D
= 54A
V
DS
= 44V
V
DS
= 28V
12
C, Capacitance (pF)
C
iss
6000
9
4000
C
oss
6
2000
C
rss
A
1
10
100
3
0
0
0
40
80
FOR TEST CIRCUIT
SEE FIGURE 13
120
160
A
200
V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10µs
I
D
, Drain Current (A)
100
100µs
100
T
J
= 175°C
T
J
= 25°C
1ms
10
10ms
10
0.4
0.8
1.2
1.6
2.0
V
GS
= 0V
2.4
A
1
1
T
C
= 25°C
T
J
= 175°C
Single Pulse
10
A
100
2.8
V
SD
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
4
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IRL2505S/LPbF
120
LIMITED BY PACKAGE
100
V
GS
R
G
5.0V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
D.U.T.
+
I
D
, Drain Current (A)
-
V
DD
80
60
40
Fig 10a.
Switching Time Test Circuit
V
DS
90%
20
0
25
50
75
100
125
150
175
T
C
, Case Temperature ( °C)
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 9.
Maximum Drain Current Vs.
Case Temperature
Fig 10b.
Switching Time Waveforms
1
Thermal Response (Z
thJC
)
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
P
DM
t
1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t
1
/ t
2
2. Peak T
J
= P
DM
x Z
thJC
+ T
C
0.0001
0.001
0.01
0.1
1
t
2
0.01
0.00001
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
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