Low Skew, 1-to-4 LVCMOS/ LVTTL-to-LVDS
Fanout Buffer
Datasheet
8545
General Description
The 8545 is a low skew, high performance 1-to-4
LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage
Differential Signaling (LVDS) the 8545 provides a low power, low
noise, solution for distributing clock signals over controlled
impedances of 100. The 8545 accepts a LVCMOS/LVTTL input
level and translates it to 3.3V LVDS output levels.
Guaranteed output and part-to-part skew characteristics make the
8545 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
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•
•
•
•
•
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•
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Four differential LVDS output pairs
Two LVCMOS/LVTTL clock inputs to support redundant
or selectable frequency fanout applications
Maximum output frequency: 650MHz
Translates LVCMOS/LVTTL input signals to LVDS levels
Output skew: 40ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 3.6ns (maximum)
Additive phase jitter, RMS: 0.13ps (typical)
Full 3.3Vsupply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN
Pullup
nD
Q
LE
CLK1
Pulldown
CLK2
Pulldown
CLK_SEL
Pulldown
0
0
1
1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
OE
Pullup
Pin Assignment
GND
CLK_EN
CLK_SEL
CLK1
nc
CLK2
nc
OE
GND
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
Q0
V
DD
Q1
Q1
Q2
Q2
GND
Q3
Q3
8545
20-Lead TSSOP
6.5mm x 4.4mm x 0.925
mm package body
G Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision C, December 8, 2015
8545 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 9, 13
2
Name
GND
CLK_EN
Power
Input
Pullup
Type
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, Q outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK2 input.
When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
No connect.
Pulldown
Pullup
Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q0/Q0 through
Q3/Q3. LVCMOS/LVTTL interface levels.
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
3
4
5, 7
6
8
10, 18
11, 12
14, 15
16, 17
19, 20
CLK_SEL
CLK1
nc
CLK2
OE
V
DD
Q3, Q3
Q2, Q2
Q1, Q1
Q0, Q0
Input
Input
Unused
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2015 Integrated Device Technology, Inc.
2
Revision C, December 8, 2015
8545 Datasheet
Function Tables
Table 3A. Control Input Function Table
Inputs
OE
0
1
1
1
1
CLK_EN
X
0
0
1
1
CLK_SEL
X
0
1
0
1
CLK1
CLK2
CLK1
CLK2
Selected Source
Q0:Q3
Hi-Z
Low
Low
Active
Active
Outputs
Q0:Q3
Hi-Z
High
High
Active
Active
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B.
Disabled
Enabled
CLK1, CLK2
CLK_EN
Q0:Q3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK1 or CLK2
0
1
Q0:Q3
LOW
HIGH
Outputs
Q0:Q3
HIGH
LOW
©2015 Integrated Device Technology, Inc.
3
Revision C, December 8, 2015
8545 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
73.2C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
52
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
CLK1, CLK2
OE, CLK_EN, CLK_SEL
CLK1, CLK2, CLK_SEL
OE, CLK_EN
CLK1, CLK2, CLK_SEL
OE, CLK_EN
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
0.8
150
5
Units
V
V
V
µA
µA
µA
µA
I
IH
I
IL
©2015 Integrated Device Technology, Inc.
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Revision C, December 8, 2015
8545 Datasheet
Table 4C. LVDS DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
I
Oz
I
OFF
I
OSD
I
OS
V
OH
V
OL
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
High Impedance Leakage
Power Off Leakage
Differential Output Short Circuit Current
Output Short Circuit Current
Output Voltage High
Output Voltage Low
0.9
-10
-20
1.125
1.25
5
±1
±1
-3.5
-3.5
1.34
1.06
Test Conditions
Minimum
200
Typical
280
Maximum
360
40
1.375
25
+10
+20
-5
-5
1.6
Units
mV
mV
V
mV
µA
µA
mA
mA
V
V
AC Electrical Characteristics
Table 5. AC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80% @ 50MHz
ƒ
266MHz
ƒ > 266MHz
200
45
40
400
ƒ
650MHz
156.25MHz, Integration
Range: 12kHz – 20MHz
1.4
0.13
40
500
700
55
60
Test Conditions
Minimum
Typical
Maximum
650
3.6
Units
MHz
ns
ps
ps
ps
ps
%
%
All parameters measured at ƒ
650MHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DD
/2 of the input to the differential output crossing point.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2015 Integrated Device Technology, Inc.
5
Revision C, December 8, 2015
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