NB100LVEP221
2.5V/3.3V 2:1:20
Differential HSTL/ECL/PECL
Clock Driver
Description
The NB100LVEP221 is a low skew 2:1:20 differential clock driver,
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The two clock inputs are differential
ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The
LVPECL input signals can be either differential configuration or
single−ended (if the V
BB
output is used).
The LVEP221 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure tightest skew, both sides of differential outputs should be
terminated identically into 50
W
even if only one output is being used.
If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The NB100LVEP221, as with most other ECL devices, can be
operated from a positive V
CC
supply in LVPECL mode. This allows the
LVEP221 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies. For more information on PECL terminations, designers should
refer to Application Note AND8020/D.
The V
BB
pin, an internally generated voltage supply, is available to this
device only. For single−ended LVPECL input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and
V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
BB
should be left open.
Single−ended CLK input operation is limited to a V
CC
≥
3.0 V in
LVPECL mode, or V
EE
≤
−3.0 V in NECL mode.
Features
www.onsemi.com
MARKING
DIAGRAMS*
52
1
NB100
LVEP221
AWLYYWWG
LQFP−52
FA SUFFIX
CASE 848H
52
1
NB100
LVEP221
AWLYYWWG
1
52
QFN−52
MN SUFFIX
CASE 485M
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
•
•
•
•
•
•
•
•
15 ps Typical Output−to−Output Skew
40 ps Typical Device−to−Device Skew
Jitter Less than 2 ps RMS
Maximum Frequency > 1.0 GHz Typical
Thermally Enhanced 52−Lead LQFP and QFN
V
BB
Output
540 ps Typical Propagation Delay
LVPECL and HSTL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= −2.375 V to −3.8 V
Q Output will Default Low with Inputs Open or at V
EE
Pin Compatible with Motorola MC100EP221
These Devices are Pb−Free and are RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
April, 2015 − Rev. 10
Publication Order Number:
NB100LVEP221/D
NB100LVEP221
V
CC0
27
26
25
24
23
22
21
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
V
CC0
20
19
18
17
16
15
14
1
2
3
4
5
6
7
8
9
10
11
12
13
Q18
Q10
Q10
Q11
29
Q19
39
V
CC0
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
40
41
42
43
44
45
46
47
48
49
50
51
52
38
37
36
35
34
33
32
31
30
NB100LVEP221
CLKSEL
CLK0
CLK1
Q19
CLK0
CLK1
V
CC0
V
CC
All V
CC
, V
CCO
, and V
EE
pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally
conductive exposed pad on package bottom (see package case drawing) must be attached to a heat−sinking conduit, capable of transfer-
ring 1.2 Watts. This exposed pad is electrically connected to V
EE
internally.
Figure 1. 52−Lead LQFP Pinout
(Top View)
www.onsemi.com
2
Q18
V
BB
V
EE
Q11
28
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
NB100LVEP221
VCC0
Q
0
Q0
Q1
Q1
Q2
Q2
Q
3
Q3
Q4
Q4
Q5
Q5
Exposed Pad (EP)
52
51
50
49
48
47
46
45
44
43
42
41
40
VCC0
VCC
CLKSEL
CLK0
CLK0
VBB
CLK1
CLK1
VEE
Q19
Q19
Q18
Q18
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
VCC0
NB100LVEP221
33
32
31
30
29
28
27
14
15
16
17
18
19
20
21
22
23
24
25
Q12
Q17
Q17
Q16
Q16
Q15
Q15
Q14
Q14
Q13
Q13
VCC0
Figure 2. 52−Lead QFN Pinout
(Top View)
Table 1. PIN DESCRIPTION
PIN
CLK0*, CLK0**
CLK1*, CLK1**
Q0:19, Q0:19
CLK_SEL*
V
BB
V
CC
/V
CCO
V
EE***
FUNCTION
ECL/PECL Differential Inputs
ECL/PECL or HSTL Differential Inputs
ECL/PECL Differential Outputs
ECL/PECL Active Clock Select Input
Reference Voltage Output
Positive Supply
Negative Supply
CLK1
V
BB
CLK_SEL
V
CC
V
EE
Active Input
CLK0, CLK0
CLK1, CLK1
CLK1
1
20
CLK0
0
CLK0
20
Q0 − Q19
Q0 − Q19
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the
package is electrically connected to V
EE
internally.
Table 2. FUNCTION TABLE
CLK_SEL
L
H
Figure 3. Logic Diagram
www.onsemi.com
3
Q12
26
NB100LVEP221
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
75 kW
37.5 kW
> 2 kV
> 200 V
> 2 kV
Pb−Free Pkg
Level 3
Level 2
UL 94 V−0 @ 0.125 in
533 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
LQFP−52
QFN−52
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Oxygen Index: 28 to 34
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(See Application Information)
Thermal Resistance (Junction−to−Case)
(See Application Information)
Thermal Resistance (Junction−to−Ambient)
(Note )
Thermal Resistance (Junction−to−Case) (Note )
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
0 lfpm
500 lfpm
0 lfpm
500 lfpm
2S2P
LQFP−52
LQFP−52
LQFP−52
LQFP−52
QFN−52
QFN−52
QFN−52
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
6
−6
6
−6
50
100
±
0.5
−40 to +85
−65 to +150
35.6
30
3.2
6.4
25
19.6
21
265
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
www.onsemi.com
4
NB100LVEP221
Table 5. LVPECL DC CHARACTERISTICS
V
CC
= 2.5 V; V
EE
= 0 V (Note 2)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended) (Note 4)
Input LOW Voltage (Single−Ended) (Note 4)
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 5)
CLK0/CLK0
CLK1/CLK1
Input HIGH Current
Input LOW Current
CLK
CLK
0.5
−150
Min
100
1355
555
1335
555
Typ
125
1480
680
Max
150
1605
900
1620
900
Min
104
1355
555
1335
555
25°C
Typ
130
1480
680
Max
156
1605
900
1620
900
Min
116
1355
555
1275
555
85°C
Typ
145
1480
680
Max
174
1605
900
1620
900
Unit
mA
mV
mV
mV
mV
1.2
0.3
2.5
1.6
150
1.2
0.3
2.5
1.6
150
1.2
0.3
2.5
1.6
150
V
V
mA
mA
I
IH
I
IL
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary + 0.125 V to −1.3 V.
3. All outputs loaded with 50
W
to V
CC
− 2.0 V.
4. Do not use V
BB
at V
CC
< 3.0 V.
5. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differen-
tial input signal.
Table 6. LVPECL DC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0 V (Note 6)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Reference Voltage (Note 8)
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
CLK0/CLK0
CLK1/CLK1
Input HIGH Current
Input LOW Current
CLK
CLK
0.5
−150
Min
100
2155
1355
2135
1355
1775
1875
Typ
125
2280
1480
Max
150
2405
1700
2420
1700
1975
Min
104
2155
1355
2135
1355
1775
1875
25°C
Typ
130
2280
1480
Max
156
2405
1700
2420
1700
1975
Min
116
2155
1355
2135
1355
1775
1875
85°C
Typ
145
2280
1480
Max
174
2405
1700
2420
1700
1975
Unit
mA
mV
mV
mV
mV
mV
1.2
0.3
3.3
1.6
150
1.2
0.3
3.3
1.6
150
1.2
0.3
3.3
1.6
150
V
V
mA
mA
I
IH
I
IL
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary + 0.925 V to −0.5 V.
7. All outputs loaded with 50
W
to V
CC
− 2.0 V.
8. Single−ended input operation is limited V
CC
≥
3.0 V in LVPECL mode.
9. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
www.onsemi.com
5
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
