Not recommended for new designs. For new designs, we recommend 6EDL04I06NT
IRS233(0,2)(D)(S&J)PbF
June 1 2011
IRS233(0,2)(D)(S & J)PbF
3-PHASE-BRIDGE DRIVER
Features
•
•
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for all channels
Over-current shutdown turns off all six drivers
Independent half-bridge drivers
Matched propagation delay for all channels
3.3 V logic compatible
Outputs out of phase with inputs
Cross-conduction prevention logic
Integrated Operational Amplifier
Integrated Bootstrap Diode function (IRS233(0,2)D)
RoHS Compliant
Product Summary
V
OFFSET
600V max.
I
O+/-
V
OUT
t
on/off
(typ.)
Deadtime (typ.)
200 mA / 420 mA
10 V – 20 V (233(0,2)(D))
500 ns
2.0 us (IRS2330(D))
0.7 us (IRS2332(D))
•
•
•
•
•
•
•
•
•
•
•
Applications:
*Motor Control
*Air Conditioners/ Washing Machines
*General Purpose Inverters
*Micro/Mini Inverter Drives
Description
The IRS233(0,2)(D)(S & J) is a high voltage, high speed
power MOSFET and IGBT driver with three independent high
and low side referenced output channels. Proprietary HVIC
technology enables ruggedized monolithic construction.
Logic inputs are compatible with CMOS or LSTTL outputs,
down to 3.3 V logic. A ground-referenced operational
amplifier provides analog feedback of bridge current via an
external current sense resistor. A current trip function which
terminates all six outputs is also derived from this resistor.
An open drain FAULT signal indicates if an over-current or
undervoltage shutdown has occurred. The output drivers
feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are
matched to simplify use at high frequencies. The floating
channel can be used to drive N-channel power MOSFET
or IGBT in the high side configuration which operates up
to 600 volts.
Packages
28-Lead SOIC
44-Lead PLCC w/o 12 Leads
Typical Connection
Absolute Maximum Ratings
www.irf.com
1
Not recommended for new designs. For new designs, we recommend 6EDL04I06NT
IRS233(0,2)(D)(S&J)PbF
Qualification Information
Qualification Level
†
††
Industrial
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
SOIC28W
MSL3 , 260°C
(per IPC/JEDEC J-STD-020)
MSL3 , 245°C
(per IPC/JEDEC J-STD-020)
†††
†††
Moisture Sensitivity Level
PLCC44
Human Body Model
ESD
Machine Model
IC Latch-Up Test
RoHS Compliant
†
††
†††
Class 2
(per JEDEC standard JESD22-A114)
Class B
(per EIA/JEDEC standard EIA/JESD22-A115)
Class I, Level A
(per JESD78)
Yes
Qualification standards can be found at International Rectifier’s web site
http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
www.irf.com
2
Not recommended for new designs. For new designs, we recommend 6EDL04I06NT
IRS233(0,2)(D)(S&J)PbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to V
SO
. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
V
B1,2,3
V
S1,2,3
V
HO1,2,3
V
CC
V
SS
V
LO1,2,3
Definition
High-side floating supply voltage
High-side floating offset voltage
High-side floating output Voltage
Low-side and logic fixed supply voltage
Logic ground
Low-side output voltage
_______ ______
Logic input voltage ( HIN1,2,3, LIN1,2,3 & ITRIP)
FAULT output voltage
Operational amplifier output voltage
Operational amplifier inverting input voltage
Allowable offset supply voltage transient
Package power dissipation @ TA ≤ +25 °C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(28 lead SOIC)
(44 lead PLCC)
(28 lead SOIC)
(44 lead PLCC)
Min.
-0.3
V
B1,2,3
- 20
V
S1,2,3
- 0.3
-0.3
V
CC
- 20
-0.3
V
SS
-0.3
Max.
620
V
B1,2,3
+ 0.3
V
B1,2,3
+ 0.3
20
V
CC
+ 0.3
V
CC
+ 0.3
(V
SS
+ 15) or
(V
CC
+ 0.3)
Whichever is
lower
V
CC
+0.3
V
CC
+0.3
V
CC
+0.3
50
1.6
2.0
78
63
150
150
300
Units
V
V
IN
V
FLT
V
CAO
V
CA-
dV
S
/dt
P
D
Rth
JA
T
J
T
S
T
L
V
SS
-0.3
V
SS
-0.3
V
SS
-0.3
—
—
—
—
—
—
-55
—
V/ns
W
°C/W
°C
www.irf.com
3
Not recommended for new designs. For new designs, we recommend 6EDL04I06NT
IRS233(0,2)(D)(S&J)PbF
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltage referenced to V
SO.
The V
S
offset rating is
tested with all supplies biased at 15 V differential.
Symbol
V
B1,2,3
V
S1,2,3
V
St1,2,3
V
HO1,2,3
V
CC
V
SS
V
LO1,2,3
V
IN
V
FLT
V
CAO
V
CA-
T
A
Definition
High-side floating supply voltage
Static high-side floating offset voltage
Transient high-side floating offset voltage
High-side floating output voltage
Low-side and Logic fixed supply voltage
Logic ground
Low-side output voltage
Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP)
FAULT output voltage
Operational amplifier output voltage
Operational amplifier inverting input voltage
Ambient temperature
Min.
V
S1,2,3
+10
V
SO
-8 (Note1)
-50 (Note2)
V
S1,2,3
10
-5
0
V
SS
V
SS
V
SS
V
SS
-40
Max.
V
S1,2,3
+20
600
600
V
B1,2,3
20
5
V
CC
V
SS
+ 5
V
CC
V
SS
+ 5
V
SS
+ 5
125
Units
V
°C
Note 1:
Logic operational for V
S
of (V
SO
-8 V) to (V
SO
+600 V). Logic state held for V
S
of (V
SO
-8 V) to (V
SO
– V
BS
)
.
Note 2:
Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to
the Application Information section of this datasheet for more details.
Note 3:
CAO input pin is internally clamped with a 5.2 V zener diode.
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS1,2,3
) = 15 V, V
SO1,2,3
= V
SS
, C
L
= 1000 pF, T
A
= 25 °C unless otherwise specified.
Symbol
t
on
t
off
t
r
t
f
t
itrip
t
bl
t
flt
t
flt, in
t
fltclr
DT
MDT
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
ITRIP to output shutdown propagation delay
ITRIP blanking time
ITRIP to FAULT indication delay
Input filter time (all six inputs)
LIN1,2,3 to FAULT clear time (2330/2)
Deadtime:
Deadtime matching: :
(IRS2330(D))
(IRS2332(D))
(IRS2330(D))
(IRS2332(D))
Min Typ Max Units Test Conditions
400
400
—
—
400
—
350
—
500
500
80
35
660
400
550
325
700
700
125
55
920
—
870
—
ns
V
IN
= 0 V & 5 V
without
external deadtime
V
IN
= 0 V & 5 V
without
external deadtime
larger than DT
PM input 10 s
V
S1,2,3
= 0 V to 600 V
V
S1,2,3
= 0 V
5300 8500 13700
1300 2000 3100
500 700 1100
—
—
400
—
—
140
—
—
—
—
50
75
MT
PM
Delay matching time (t
ON
, t
OFF
)
Pulse width distortion
NOTE:
For high side PWM, HIN pulse width must be > 1.5 usec
www.irf.com
4
Not recommended for new designs. For new designs, we recommend 6EDL04I06NT
IRS233(0,2)(D)(S&J)PbF
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS1,2,3
) = 15 V, V
SO1,2,3
= V
SS
, C
L
= 1000 pF, T
A
= 25 °C unless otherwise specified.
Symbol
SR+
SR-
Definition
Operational amplifier slew rate (+)
Operational amplifier slew rate (-)
Min Typ Max Units Test Conditions
5
2.4
10
3.2
—
—
V/ s
1 V input step
www.irf.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
