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- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
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© Nexperia B.V. (year). All rights reserved.
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74AHC594; 74AHCT594
8-bit shift register with output register
Rev. 02 — 9 June 2008
Product data sheet
1. General description
The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register
that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct
overriding clears (SHR and STR) are provided on both the shift and storage registers.
A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register will always be one count pulse ahead of the
storage register.
2. Features
I
I
I
I
I
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Wide supply voltage range from 2.0 V to 5.5 V
8-bit serial-in, parallel-out shift register with storage
Independent direct overriding clears on shift and storage registers
Independent clocks for shift and storage registers
Latch-up performance exceeds 100 mA per JESD78 Class II
Input levels:
N
For 74AHC594: CMOS level
N
For 74AHCT594: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Applications
I
Serial-to parallel data conversion
I
Remote control holding register
NXP Semiconductors
74AHC594; 74AHCT594
8-bit shift register with output register
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC594
74AHC594D
74AHC594DB
74AHC594PW
74AHC594BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO16
SSOP16
TSSOP16
DHVQFN16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT338-1
SOT403-1
Description
Version
Type number
plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT338-1
SOT403-1
74AHCT594
74AHCT594D
74AHCT594DB
74AHCT594PW
74AHCT594BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO16
SSOP16
TSSOP16
DHVQFN16
plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
5. Functional diagram
DS
SHCP
SHR
14
11
10
9
12
13
8-BIT STORAGE REGISTER
Q7S
8-STAGE SHIFT REGISTER
STCP
STR
15 1
2
3
4
5
6
7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
mbc320
Fig 1.
Functional diagram
74AHC_AHCT594_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 June 2008
2 of 22
NXP Semiconductors
74AHC594; 74AHCT594
8-bit shift register with output register
SHCP STCP
STR
11
12
9
15
1
2
DS
14
3
4
5
6
7
10
SHR
13
STR
mbc319
mbc322
13
12
10
11
14
R1 SRG8
C1/
1D
R2
C2
STCP
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DS
SHR
SHCP
2D
15
1
2
3
4
5
6
7
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7S
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
STAGE 0
DS
D
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
Q
Q7S
FFSH0
CP
R
SHCP
FFSH7
CP
R
SHR
D
Q
D
CP
Q
FFST0
CP
R
STCP
FFST7
R
STR
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
mbc321
Fig 4.
Logic diagram
74AHC_AHCT594_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 June 2008
3 of 22
NXP Semiconductors
74AHC594; 74AHCT594
8-bit shift register with output register
6. Pinning information
6.1 Pinning
74AHC594
74AHCT594
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
001aae343
16 V
CC
15 Q0
14 DS
13 STR
12 STCP
11 SHCP
10 SHR
9
Q7S
Fig 5.
Pin configuration SO16
74AHC594
74AHCT594
terminal 1
index area
Q2
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
001aae344
74AHC594
74AHCT594
16 V
CC
15 Q0
14 DS
13 STR
12 STCP
11 SHCP
10 SHR
9
Q7S
2
3
4
5
6
7
8
GND
Q7S
9
GND
(1)
16 V
CC
15 Q0
14 DS
13 STR
12 STCP
11 SHCP
10 SHR
Q3
Q4
Q5
Q6
Q7
1
Q1
001aae345
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 6.
Pin configuration (T)SSOP16
Fig 7.
Pin configuration DHVQFN16
74AHC_AHCT594_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 June 2008
4 of 22
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