74AUP1T97
Rev. 6 — 28 March 2017
Low-power configurable gate with voltage-level translator
Product data sheet
1
General description
The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected
to V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 2.3 V to 3.6 V.
The 74AUP1T97 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire V
CC
range.
2
Features and benefits
•
Wide supply voltage range from 2.3 V to 3.6 V
•
High noise immunity
•
ESD protection:
–
HBM JESD22-A114F Class 3A exceeds 5 000 V
–
MM JESD22-A115-A exceeds 200 V
–
CDM JESD22-C101E exceeds 1 000 V
•
Low static power consumption; I
CC
= 1.5 μA (maximum)
•
Latch-up performance exceeds 100 mA per JESD 78 Class II
•
Inputs accept voltages up to 3.6 V
•
Low noise overshoot and undershoot < 10 % of V
CC
•
I
OFF
circuitry provides partial power-down mode operation
•
Multiple package options
•
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
Low-power configurable gate with voltage-level translator
74AUP1T97
3
Ordering information
Package
Temperature
range
Name
SC-88
XSON6
XSON6
XSON6
XSON6
Table 1. Ordering information
Type number
Description
plastic surface-mounted package; 6 leads
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 x 1 x 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
Version
SOT363
SOT886
SOT891
SOT1115
SOT1202
SOT1255
74AUP1T97GW
74AUP1T97GM
74AUP1T97GF
74AUP1T97GN
74AUP1T97GS
74AUP1T97GX
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
X2SON6 plastic thermal extremely thin small
outline package; no leads; 6 terminals;
body 1 x 0.8 x 0.35 mm
WLCSP6 wafer level chip-scale package; 6 bumps;
0.65 x 0.44 x 0.27 mm
74AUP1T97UK
-40 °C to +125 °C
SOT1454-1
4
Marking
Marking code
59
59
59
59
59
59
9
[1]
Table 2. Marking
Type number
74AUP1T97GW
74AUP1T97GM
74AUP1T97GF
74AUP1T97GN
74AUP1T97GS
74AUP1T97GX
74AUP1T97UK
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74AUP1T97
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 6 — 28 March 2017
2 / 23
Nexperia
Low-power configurable gate with voltage-level translator
74AUP1T97
5
Pinning information
5.1 Pinning
Table 3. Pinning
74AUP1T97
74AUP1T97
B
GND
A
1
2
3
001aag500
B
1
6
C
6
5
4
C
V
CC
GND
2
5
V
CC
Y
A
3
4
Y
001aag501
Transparent top view
Figure 1. Pin configuration SOT363 (SC-88)
74AUP1T97
B
GND
A
1
2
3
6
5
4
C
V
CC
Y
Figure 2. Pin configuration SOT886 (XSON6)
74AUP1T97
B
1
GND
3
A
2
5
4
Y
C
6
V
CC
001aag502
Transparent top view
aaa-019832
Transparent top view
Figure 3. Pin configuration SOT891, SOT1115 and
SOT1202 (XSON6)
ball A1
index area
A
Figure 4. Pin configuration SOT1255 (X2SON6)
74AUP1T97UK
1
A
B
2
C
74AUP1T97UK
1
2
B
B
GND
V
CC
Y
aaa-018293
C
aaa-018292
C
A
Transparent top view
Transparent top view
Figure 5. Pin configuration SOT1454-1 (WLCSP6)
Figure 6. Ball mapping for SOT1454-1 (WLCSP6)
74AUP1T97
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 6 — 28 March 2017
3 / 23
Nexperia
Low-power configurable gate with voltage-level translator
74AUP1T97
5.2 Pin description
Table 4. Pin description
Symbol
B
GND
A
Y
V
CC
C
Pin
SC88, XSON6 and X2SON6
1
2
3
4
5
6
Description
WLCSP6
A1
B1
C1
C2
B2
A2
data input
ground (0 V)
data input
data output
supply voltage
data input
6
Functional description
[1]
Table 5. Function table
Input
C
L
L
L
L
H
H
H
H
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
L
H
H
L
H
L
H
H = HIGH voltage level; L = LOW voltage level.
7
Functional diagram
A
3
4
B
1
Y
C
6
001aad998
Figure 7. Logic symbol
74AUP1T97
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 6 — 28 March 2017
4 / 23
Nexperia
Low-power configurable gate with voltage-level translator
74AUP1T97
8
Logic configurations
Figure
see
Figure 8
see
Figure 9
see
Figure 10
see
Figure 10
see
Figure 11
see
Figure 11
see
Figure 12
see
Figure 13
see
Figure 14
V
CC
B
A
C
B
Y
A
1
2
3
6
5
4
Y
001aae002
Table 6. Function selection table
Logic function
2-input MUX
2-input AND
2-input OR with one input inverted
2-input NAND with one input inverted
2-input AND with one input inverted
2-input NOR with one input inverted
2-input OR
Inverter
Buffer
V
CC
1
A
C
Y
A
2
3
6
5
4
Y
001aae003
C
C
Figure 8. 2-input MUX
V
CC
A
C
A
C
Figure 9. 2-input AND gate
V
CC
B
C
B
C
Y
1
2
6
5
4
C
Y
B
1
2
6
5
4
C
Y
A
3
Y
001aae004
Y
3
Y
001aae005
Figure 10. 2-input NAND gate with input A inverted or 2-
input OR gate with input C inverted
V
CC
B
B
C
Y
1
2
3
6
5
4
Y
001aae006
Figure 11. 2-input NOR gate with input B inverted or 2-
input AND gate with input C inverted
V
CC
C
1
C
Y
2
3
6
5
4
C
Y
001aae007
Figure 12. 2-input OR gate
Figure 13. Inverter
74AUP1T97
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 6 — 28 March 2017
5 / 23
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