MB9B160R Series
32-bit ARM
®
Cortex
®
-M4F
FM4 Microcontroller
The MB9B160R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and
competitive cost.
These series are based on the ARM
®
Cortex
®
-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions
such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I
2
C, LIN).
Features
32-bit ARM
®
Cortex
®
-M4F Core
Processor version: r0p1
Up to 160 MHz Frequency Operation
FPU built-in
Support DSP instruction
Memory Protection Unit (MPU): improves the reliability of an
embedded system
[SRAM]
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to I-code bus or
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
SRAM0: Up to 64 Kbytes
SRAM1: Up to 32 Kbytes
SRAM2: Up to 32 Kbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-bit Data width
Up to 25-bit Address bit
Maximum Access size: 256M byte
Supports Address/Data multiplex
Supports external RDY function
Supports scramble function
Possible to set the validity/invalidity of the scramble function
for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4
Mbytes units.
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash
memories.
MainFlash memory
Up
to 1024 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
The read access to Flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to Flash memory can be obtained by
Flash Accelerator System.
Security function for code protection
Possible to set two kinds of the scramble key
Note: It is necessary to prepare the dedicated software
library to use the scramble function.
WorkFlash memory
32
Multi-function Serial Interface (Max 8 channels)
64 bytes with FIFO (the FIFO step numbers are variable
depending on the settings of the communication mode or bit
length.)
Kbytes
cycle:
• 6 wait-cycle: the operation frequency more than 120
MHz, and up to 160 MHz
• 4 wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
• 2 wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
• 0 wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
Read
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I
2
C
Cypress Semiconductor Corporation
Document Number: 002-04918 Rev.*C
• 198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 16, 2017
MB9B160R Series
DSTC (Descriptor System data Transfer Controller)
(128 channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the Descriptor system and,
following the specified contents of the Descriptor which has
already been constructed on the memory, can access directly
the memory /peripheral device and performs the data transfer
operation.
It supports the software activation, the hardware activation and
the chain activation functions.
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 3 units
Conversion time: 0.5 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch.6 and ch.7 only)
Supports high-speed SPI (ch.4 and ch.6 only)
Data length 5 to 16-bit
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generation (can change to 13 to 16-bit
length)
DA converter (Max 2 channels)
R-2R type
12-bit resolution
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
LIN break delimiter generation (can change to 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as general purpose I/O ports when
they are not used for external bus or peripherals. Moreover,
the port relocate function is built in. It can set which I/O port
the peripheral function can be allocated.
[I
2
C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
Fast-mode Plus (Fm+) (Max 1000 kbps, only for ch.3 = ch.A
and ch.7 = ch.B) supported
DMA Controller (8 channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-
in peripherals
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 100 high-speed general-purpose I/O ports @ 120 pin
Package
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Some pin is 5V tolerant I/O.
See “Pin Description” and “I/O Circuit Type” for the
corresponding pins.
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
Document Number: 002-04918 Rev.*C
Page 2 of 160
MB9B160R Series
Multi-function Timer (Max 2 units)
The Multi-function timer is composed of the following blocks.
Minimum resolution: 6.25 ns
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 6 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
Free-running
Periodic ( = Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in high-speed CR clock or built-in low-speed CR
clock as the clock source.
Interval timer: up to 64s (Max) @ Sub Clock: 32.768 kHz
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
External Interrupt Controller Unit
External interrupt input pin: Max 16 pins
Include one non-maskable interrupt (NMI)
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC)
(Max 2 channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
SD Card Interface
It is possible to use the SD card that conforms to the following
standards.
The detection edge of the three external event input pins
AIN, BIN and ZIN is configurable.
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version
3.00
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
1-bit or 4-bit data bus
Document Number: 002-04918 Rev.*C
Page 3 of 160
MB9B160R Series
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Low-power Consumption Mode
Six low-power consumption modes are supported.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable from with/without RAM
retention)
Main clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
High-speed internal CR Clock: 4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
Deep standby stop (selectable from with/without RAM
retention)
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
RTC
32 kHz oscillation circuit
Power-on circuit
Back up register: 32 bytes
Port circuit
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
Unique ID
Unique value of the device (41-bit) is set.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Power Supply
Two Power Supplies
Wide range voltage:
Power supply for VBAT:
VCC
VBAT
=
=
2.7 V to 5.5 V
2.7 V to 5.5 V
Document Number: 002-04918 Rev.*C
Page 4 of 160
MB9B160R Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. Pin Description ................................................................................................................................................................ 15
5. I/O Circuit Type................................................................................................................................................................ 43
6. Handling Precautions ..................................................................................................................................................... 50
6.1
Precautions for Product Design ................................................................................................................................... 50
6.2
Precautions for Package Mounting .............................................................................................................................. 51
6.3
Precautions for Use Environment ................................................................................................................................ 52
7. Handling Devices ............................................................................................................................................................ 53
8. Block Diagram ................................................................................................................................................................. 56
9. Memory Size .................................................................................................................................................................... 57
10. Memory Map .................................................................................................................................................................... 57
11. Pin Status in Each CPU State ........................................................................................................................................ 60
12. Electrical Characteristics ............................................................................................................................................... 67
12.1 Absolute Maximum Ratings ......................................................................................................................................... 67
12.2 12.2 Recommended Operating Conditions.................................................................................................................. 68
12.3 DC Characteristics....................................................................................................................................................... 71
12.3.1 Current Rating .............................................................................................................................................................. 71
12.3.2 Pin Characteristics ....................................................................................................................................................... 79
12.4 AC Characteristics ....................................................................................................................................................... 81
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 81
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 82
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 82
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) ......................................... 83
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) .... 83
12.4.6 Reset Input Characteristics .......................................................................................................................................... 83
12.4.7 Power-on Reset Timing................................................................................................................................................ 84
12.4.8 GPIO Output Characteristics ........................................................................................................................................ 84
12.4.9 External Bus Timing ..................................................................................................................................................... 85
12.4.10 Base Timer Input Timing........................................................................................................................................... 96
12.4.11 CSIO/UART Timing .................................................................................................................................................. 97
12.4.12 External Input Timing .............................................................................................................................................. 130
12.4.13 Quadrature Position/Revolution Counter Timing .................................................................................................... 131
12.4.14 I
2
C Timing ............................................................................................................................................................... 133
12.4.15 SD Card Interface Timing ....................................................................................................................................... 135
12.4.16 ETM Timing ............................................................................................................................................................ 137
12.4.17 JTAG Timing ........................................................................................................................................................... 138
12.5 12-bit A/D Converter .................................................................................................................................................. 139
12.6 12-bit D/A Converter .................................................................................................................................................. 142
12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 143
12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 143
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 143
12.8 MainFlash Memory Write/Erase Characteristics ........................................................................................................ 144
12.9 WorkFlash Memory Write/Erase Characteristics ....................................................................................................... 144
12.10 Standby Recovery Time ............................................................................................................................................ 145
12.10.1 Recovery cause: Interrupt/WKUP ........................................................................................................................... 145
Document Number: 002-04918 Rev.*C
Page 5 of 160
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