CYW20733
Single-Chip Bluetooth Transceiver
Wireless Input Devices
The Cypress CYW20733 is a Bluetooth 3.0 + EDR compliant, stand-alone baseband processor with an integrated 2.4 GHz trans-
ceiver. The device is ideal for applications in wireless input devices including game controllers, keyboards, and joysticks. Built-in
firmware adheres to the Bluetooth Human Interface Device (HID) profile and Bluetooth Device ID profile specifications. The
CYW20733 radio has been designed to provide low power, low cost, and robust communications for applications operating in the
globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification 3.0 + EDR. The single-
chip Bluetooth transceiver is a monolithic component implemented in a standard digital CMOS process and requires minimal exter-
nal components to make a fully compliant Bluetooth device. The CYW20733 is available in three package options: a 81-pin, 8 mm ×
8 mm FBGA, a 121-pin, 9 mm × 9 mm FBGA, and a 56-pin, 7 mm x 7 mm QFN.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
BCM20733
BCM20733A3KFB1G
BCM20733A3KFB2G
BCM20733A3KML1G
Cypress Part Number
CYW20733
CYW20733A3KFB1G
CYW20733A3KFB2G
CYW20733A3KML1G
Features
Integrated LDO to reduce BOM cost
■
Bluetooth specification 3.0 + EDR compatible
■
Bluetooth HID profile version 1.1 compliant
■
Bluetooth Device ID profile version 1.3 compliant
■
Supports AFH
■
Excellent receiver sensitivity
■
On-chip support for common keyboard and mouse inter-
faces eliminates external processor
■
Infrared (IR) modulator
■
IR learning
■
Integrated 200 mW filterless Class-D audio amplifier
■
Triac control
■
Triggered Broadcom Fast Connect
■
One I/O capable of sinking 100 mA for high- current drive
applications
■
Programmable key scan matrix interface, up to 8 × 20 key-
scanning matrix
■
Three-axis quadrature signal decoder
■
On-chip support for serial peripheral interface (master and
slave modes)
■
Broadcom Serial Communications Interface (compatible
with Philips® I2C slaves)
■
Two independent half-duplex PCM/I2S interfaces
■
Real-time clock supported with 32.768 kHz oscillator
■
Programmable output power control meets Class 2 or
Class 3 requirements
■
On-chip PA with a maximum output power of +10dBm with-
out external component
■
Integrated ARM7TDMI-S™-based microprocessor core
■
On-chip power on reset (POR)
■
On-chip software control power management unit
■
Three package types available:
❐
81-pin FBGA package (8 mm × 8 mm)
❐
121-pin FBGA package (9 mm × 9 mm)
❐
56-pin QFN package (7 mm x 7 mm)
■
RoHS compliant
■
■
■
■
■
Applications
■
■
■
■
Game controllers
Wireless pointing devices: mice, trackballs
Wireless keyboards
Joysticks
Point-of-sale (POS) input devices
Remote controls
Home automation
3D glasses
Cypress Semiconductor Corporation
Document No. 002-14859 Rev. *S
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 9, 2017
CYW20733
Figure 1. Functional Block Diagram
Muxed on GPIO
Tx
Rx
RTSN
Tx
RTSN
MISO
SDA/
CTSN
MOSI
SCK
CTSN Rx
1.2V
VDDC
VSS,
VDDO,
VDDC
Speaker
WDT
Processing
Unit
(ARM7)
Test
UART
Periph
UART
BSC/SPI
Master
Interface
(BSC is I2C-
compat)
28 ADC
Inputs
1.2V
POR
Digital
Audio
Block
Class-D
Driver
CT
ADC
1.2V VDDC
Domain
MIA
POR
3V
Speaker
Out
System Bus
32 kHz
LPCLK
24 MHz
1.62V -3.6V
1.2V
LDO
384K
ROM
80K
RAM
Peripheral
Interface
Block
Volt. Trans
I/O Ring
Control
Registers
LDO
CTRL
1.2V
RF Control
and Data
2.4 GHz
Radio
Power
Bluetooth
Baseband
Core
I/O Ring Bus
GPIO
Control/
Status
Registers
32 kHz
LPCLK
24 MHz
RF I/O
T/R
Switch
Frequency
Synthesizer
IR
Mod.
and
Learning
Keyboard
Matrix
Scanner
w/FIFO
3-Axis
Mouse
Signal
Controller
SPI
M/S
PWM
PMU
WAKE
IR
57 GPIO I/O
8 x 20 6 quadrature inputs
Scan (3 pair) + Hi -current
Matrix Driver Controls
28 ADC
Inputs
÷4
AutoCal
1.2V VDDRF
Domain
High
Sink IO
VDDO Domain
128 kHz
LPCLK
128 kHz
LPO
Ref Xtal
57 GPIO Pins
32 kHz Xtal (op onal)
Document No. 002-14859 Rev. *S
Page 2 of 67
CYW20733
Contents
1.Functional Description ....................................... 4
1.1
Integrated Radio Transceiver .............................. 4
1.1.1 Transmitter Path ...................................... 4
1.1.2 Receiver Path .......................................... 4
1.1.3 Local Oscillator ........................................ 4
1.1.4 Calibration ............................................... 4
1.1.5 Internal LDO Regulator ............................ 4
Microprocessor Unit ............................................ 5
1.2.1 EEPROM Interface .................................. 5
1.2.2 Serial Flash Interface ............................... 5
1.2.3 Internal Reset .......................................... 5
1.2.4 External Reset ......................................... 6
1.3
Bluetooth Baseband Core ................................... 6
1.3.1 Frequency Hopping Generator ................ 6
1.3.2 E0 Encryption .......................................... 6
1.3.3 Link Control Layer ................................... 6
1.3.4 Adaptive Frequency Hopping .................. 6
1.3.5 Bluetooth Version 3.0 Features ............... 6
1.3.6 Test Mode Support .................................. 7
1.4
Peripheral Transport Unit (PTU) ......................... 7
1.4.1 Broadcom Serial Control Interface .......... 7
1.4.2 UART Interface ........................................ 8
1.5
PCM Interface ..................................................... 9
1.5.1 System Diagram ...................................... 9
1.5.2 Slot Mapping .......................................... 10
1.5.3 Frame Synchronization .......................... 10
1.5.4 Data Formatting ..................................... 10
1.6
1.7
1.8
1.9
I
2
S Interface ...................................................... 10
Clock Frequencies ............................................ 10
1.7.1 Crystal Oscillator ................................... 10
GPIO Port .......................................................... 12
Keyboard Scanner ............................................ 12
1.9.1 Theory of Operation ............................... 13
1.14 Infrared Modulator ..............................................18
1.15 Infrared Learning ................................................19
1.16 Shutter Control for 3D Glasses ..........................19
1.17 Triac Control .......................................................20
1.18 Cypress Proprietary Control Signalling
and Triggered Broadcom Fast Connect .............20
1.19 Integrated Filterless Class-D Audio Amplifier .....20
1.20 High-Current I/O .................................................21
1.21 Power Management Unit ....................................22
1.21.1 RF Power Management ..........................22
1.21.2 Host Controller Power Management ......22
1.21.3 BBC Power Management .......................22
1.2
2.Pin Assignments............................................... 23
2.1
Ball Maps ...........................................................29
2.1.1 81-Pin FBGA Ball Map ...........................29
2.1.2 121-Pin FBGA Ball Map .........................31
2.1.3 56-Pin QFN Diagram ..............................32
Electrical Characteristics ....................................33
RF Specifications ...............................................37
Timing and AC Characteristics ...........................39
3.3.1 UART Timing ..........................................39
3.3.2 SPI Timing ..............................................40
3.3.3 BSC Interface Timing .............................41
3.3.4 PCM Interface Timing .............................43
3.3.5 I
2
S Timing ...............................................48
3.Specifications.................................................... 33
3.1
3.2
3.3
4.Mechanical Information.................................... 53
4.0.1 Tape Reel and Packaging
Specifications .........................................56
5.Ordering Information ........................................ 62
6.IoT Resources ................................................... 62
A.Acronyms and Abbreviations.......................... 62
Document History........................................................... 64
Sales, Solutions, and Legal Information ...................... 67
1.10 Mouse Quadrature Signal Decoder ................... 13
1.10.1 Theory of Operation ............................... 13
1.11 ADC Port ........................................................... 13
1.12 PWM ................................................................. 14
1.13 Serial Peripheral Interface ................................. 15
Document No. 002-14859 Rev. *S
Page 3 of 67
CYW20733
1. Functional Description
1.1 Integrated Radio Transceiver
The CYW20733 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has
been designed to provide low power, low cost, robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 + EDR and meets or exceeds the requirements to
provide the highest communication link quality of service.
1.1.1 Transmitter Path
The CYW20733 features a fully integrated zero IF transmitter. The baseband transmit data is GFSK modulated in the modem block
and upconverted to the 2.4 GHz ISM band. The transmit path consists of signal filtering,
I/Q upconversion, output power amplification, and RF filtering. It also incorporates the
/4-DQPSK
and 8-DPSK modulation schemes,
which support the 2 Mbps and 3 Mbps enhanced data rates, respectively.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK,
/4-DQPSK,
and
8-DPSK signals. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the
transmitted signal and is much more stable than direct VCO modulation schemes.
Power Amplifier
The integrated power amplifier (PA) for the CYW20733 can transmit at a maximum power of +4 dBm for class 2 operation. The transmit
power levels are for basic rate and EDR. Due to the linear nature of the PA, combined with some integrated filtering, no external filters
are required for meeting Bluetooth and regulatory harmonic and spurious requirements.
The CYW20733 internal PA can deliver a maximum output power of +10 dBm for basic rate and +8 dBm for EDR with a flexible supply
range of 2.5V to 3.0V.
1.1.2 Receiver Path
The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation
enables the CYW20733 to be used in most applications without off-chip filtering.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the CYW20733 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller
to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
1.1.3 Local Oscillator
The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO
subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW20733 uses an internal RF and IF
loop filter.
1.1.4 Calibration
The CYW20733 radio transceiver features an automated calibration scheme that is self-contained in the radio. No user interaction is
required during normal operation or during manufacturing to provide the optimal performance. Calibration will optimize the gain and
phase performance of all the major blocks within the radio to within 2% of optimal conditions. Calibrated blocks include filters, the
matching networks between key components, and key gain blocks. The calibration process corrects for both process and temperature
variations. It occurs transparently during normal operation and the setting time of the hops and will calibrate for temperature variations
as the device cools and heats during normal operation in its environment.
1.1.5 Internal LDO Regulator
To reduce the external BOM, the CYW20733 has an integrated 1.2V LDO regulator to provide power to the digital and RF circuits and
system components. The 1.2V LDO regulator operates from a 1.62V to 3.63V input supply with a 60 mA maximum load current.
In noisy environments, a ferrite bead may be needed between the digital and RF supply pins to isolate noise coupling and suppress
noise into the RF circuits.
Note:
Always place the decoupling capacitors near the pins as close together as possible.
Document No. 002-14859 Rev. *S
Page 4 of 67
CYW20733
1.2 Microprocessor Unit
The CYW20733 microprocessor unit (µPU) runs software from the link control (LC) layer up to the Human Interface Device (HID). The
microprocessor is based on an ARM7™ 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The µPU
has 320 KB of ROM for program storage and boot-up, 80 KB of RAM for scratch-pad data, and patch RAM code.
The internal boot ROM allows for flexibility during power-on reset to enable the same device to be used in various configurations,
including UART, and with an external serial EEPROM or with an external flash memory. At power-up, the lower layer protocol stack
is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can
also support the integration of user applications.
1.2.1 EEPROM Interface
The CYW20733 provides the BSC (Broadcom Serial Control) master interface; the BSC is programmed by the CPU to generate four
different types of BSC transfers on the bus: read-only, write-only, combined read/write, and combined write/read. BSC supports both
low-speed and fast mode devices. The BSC is compatible with a Philips® I
2
C slave device, except that master arbitration (multiple
I
2
C masters contending for the bus) is not supported. Native support for Microchip® 24LC128, Microchip 24AA128, and STMicroelec-
tronics® M24128-BR is included.
The EEPROM can contain customer application configuration information, including: application code, configuration data, patches,
pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.
1.2.2 Serial Flash Interface
The CYW20733 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB
slave interface, transmit and receive FIFOs, and the SPI core PHY logic.
Devices natively supported include the following:
■
■
Atmel® AT25BCM512B
MXIC MX25V512ZUI-20G
1.2.3 Internal Reset
The CYW20733 has an integrated power-on reset circuit that resets all circuits to a known power-on state.
Figure 1. Internal Reset Timing
VDDO POR delay
~ 2 ms
VDDO
VDDO POR threshold
VDDO POR
VDDC POR threshold
VDDC
VDDC POR delay
~ 2 ms
VDDC POR
Crystal
warm‐up
delay:
~ 5 ms
Start reading EEPROM and firmware boot.
Baseband Reset
Crystal Enable
Document No. 002-14859 Rev. *S
Page 5 of 67
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