74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 250MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT74B
74ACT74M
DESCRIPTION
The 74ACT74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS tecnology.
A signal on the D INPUT is transferred to the Q
and Q OUTPUTS during the positive going
transition of the clock pulse.
PIN CONNECTION AND IEC LOGIC SYMBOLS
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CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
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T&R
74ACT74MTR
74ACT74TTR
April 2001
1/12
74ACT74
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
200
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
T
stg
Storage Temperature
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
Parameter
Value
4.5 to 5.5
0 to V
CC
0 to V
CC
8
1) V
IN
from 0.8V to 2.0V
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-55 to 125
od
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Unit
V
V
V
°C
ns/V
3/12
74ACT74
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Low Level Output
Voltage
4.5
5.5
4.5
5.5
I
I
I
CCT
I
CC
I
OLD
I
OHD
Input Leakage Cur-
rent
Max I
CC
/Input
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
5.5
5.5
5.5
5.5
V
O
= 0.1 V or
V
CC
-0.1V
V
O
= 0.1 V or
V
CC
-0.1V
I
O
=-50
µA
I
O
=-50
µA
I
O
=-24 mA
I
O
=-24 mA
I
O
=50
µA
I
O
=50
µA
I
O
=24 mA
I
O
=24 mA
V
I
= V
CC
or GND
V
I
= V
CC
- 2.1V
V
I
= V
CC
or GND
V
OLD
= 1.65 V max
V
OHD
= 3.85 V min
0.6
4
4.4
5.4
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
±
0.1
T
A
= 25°C
Min.
2.0
2.0
Typ.
1.5
1.5
1.5
1.5
4.49
5.49
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Max.
Value
-40 to 85°C
Min.
2.0
2.0
0.8
0.8
4.4
5.4
3.7
4.7
0.1
0.1
V
Max.
-55 to 125°C
Min.
2.0
2.0
0.8
0.8
V
Max.
V
Unit
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
bs
O
t
PLH
t
PHL
Propagation Delay
Time CK to Q or Q
t
PLH
t
PHL
Propagation Delay
Time PR or CLR to
Q or Q
t
W
Pulse Width HIGH
or LOW, CK or PR
or CLR
Setup Time D to CK
t
s
HIGH or LOW
t
h
Hold Time D to CK
HIGH or LOW
t
REM
Removal Tim|
PR or CLR to CK
f
MAX
Maximum Clock
Frequency
et
l
o
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d
V
CC
(V)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
s)
t(
so
b
-O
Min.
5.0
5.0
te
le
r
P
od
1.5
40
75
-75
±
1
s)
t(
uc
0.5
0.5
±
1
1.6
40
50
-50
µA
mA
µA
mA
mA
Value
-40 to 85°C
Min.
Max.
11.0
11.0
-55 to 125°C
Min.
Max.
11.0
11.0
ns
ns
Unit
T
A
= 25°C
Typ.
Max.
10.0
10.0
1.5
0.5
-0.5
-0.7
100
250
5.0
3.0
1.0
1.0
85
6.0
3.5
1.0
1.0
85
6.0
3.5
1.0
1.0
ns
ns
ns
ns
MHz
(*) Voltage range is 5.0V
±
0.5V
4/12
74ACT74
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
f
IN
= 10MHz
T
A
= 25°C
Min.
Typ.
3
43
Max.
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per
Flip-Flop)
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
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