Dual 2:1, 1:2 Differential-to-LVPECL/ECL
Multiplexer
ICS853S54I
DATA SHEET
General Description
The ICS853S54I is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplex-
er allows one of 2 inputs to be selected onto one output pin and the
1:2 MUX switches one input to one of two outputs. This device is
useful for multiplexing multi-rate Ethernet PHYs which have 100 M
bit and 1000 bit transmit/receive pairs onto an optical SFP module
which has a single transmit/receive pair. See Application Section for
further information.
The ICS853S54I is optimized for applications requiring very high
performance and has a maximum operating frequency of 2.5GHz.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
•
•
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•
•
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Three differential LVPECL output pairs
Three differential LVPECL clock inputs
PCLKx/nPCLKx pairs can accept the following differential input
levels: LVPECL, LVDS, CML
Maximum output frequency: 2.5GHz
Part-to-part skew: 200ps (maximum)
Propagation delay: QA, nQA: 450ps (maximum)
QBx, nQBx: 420ps (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.465V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Block Diagram
CLK_SELA
Pulldown
Pin Assignment
CLK_SELA
nQA
V
CC
QA
PCLKA0
Pulldown
nPCLKA0
Pullup/Pulldown
PCLKA1
Pulldown
nPCLKA1
Pullup/Pulldown
0
QA
nQA
1
QB0 1
nQB0
2
16 15 14 13
12 PCLKA0
11 nPCLKA0
10 PCLKA1
9 nPCLKA1
5
PCLKB
QB1 3
nQB1 4
6
nPCLKB
7
CLK_SELB
8
V
EE
PCLKB
Pulldown
nPCLKB
Pullup/Pulldown
QB0
nQB0
ICS853S54I
CLK_SELB
Pulldown
QB1
nQB1
16-Lead VFQFN
Top View
ICS853S54AKI May 27, 2017
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©2017 Integrated Device Technology, Inc.
ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5
6
7
8
9
10
11
12
13
14
15, 16
Name
QB0, nQB0
QB1, nQB1
PCLKB
nPCLKB
CLK_SELB
V
EE
nPCLKA1
PCLKA1
nPCLKA0
PCLKA0
V
CC
CLK_SELA
nQA, QA
Output
Output
Input
Input
Input
Power
Input
Input
Input
Input
Power
Input
Output
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Non-inverting LVPECL/ECL differential clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Clock select pin for QBx outputs. When HIGH, selects QB1/nQB1 outputs.
When LOW, selects QB0/nQB0 outputs. LVCMOS/LVTTL interface levels.
Negative supply pin.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inverting LVPECL/ECL differential clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inverting LVPECL/ECL differential clock input.
Positive supply pin.
Clock select pin for QA output. When HIGH, selects QA output. When LOW,
selects nQA output. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL/ECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
VCC/2
Parameter
Input Capacitance
Input Pullup Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
37.5
37.5
Maximum
Units
pF
k
k
Function Tables
Table 3A. Control Input Function Table, (Bank A)
Bank A
Control Input
CLK_SELA
0 (default)
1
Outputs
QA, nQA
Selects PCLKA0, nPCLKA0
Selects PCLKA1, nPCLKA1
Control Input
CLK_SELB
0 (default)
1
Outputs
QB0, nQB0
Follows PCLKB input
Logic Low
QB1, nQB1
Logic Low
Follows PCLKB input
Table 3B. Control Input Function Table, (Bank B)
Bank B
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©2017 Integrated Device Technology, Inc.
ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
Operating Termperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
JA
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-4.6V (ECL mode, V
CC
= 0V)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
– 0.5V
50mA
100mA
-40C to 85C
-65C to 150C
74.7C/W (0 mps)
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= 2.375V to 3.465V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
45
Units
V
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, V
CC
= 2.375V to 3.465V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SELA,
CLK_SELB
CLK_SELA,
CLK_SELB
V
CC
= V
IN
V
CC
= V
IN
-150
Test Conditions
Minimum
0.7V
CC
-0.3
Typical
Maximum
V
CC
+ 0.3
0.3V
CC
150
Units
V
V
μA
μA
Table 4C. LVCMOS/LVTTL DC Characteristics, V
CC
= 0V, V
EE
= -3.465V to -2.375V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SELA,
CLK_SELB
CLK_SELA,
CLK_SELB
V
CC
= V
IN
V
CC
= V
IN
-150
Test Conditions
Minimum
0.3V
EE
V
EE
– 0.3
Typical
Maximum
0.3
0.7V
EE
150
Units
V
V
μA
μA
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©2017 Integrated Device Technology, Inc.
ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Table 4D. LVPECL DC Characteristics, V
CC
= 2.375V to 3.465V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input
High Current
Input
Low Current
PCLKA[0:1], PCLKB
nPCLKA[0:1], nPCLKB
PCLKA[0:1], PCLKB
nPCLKA[0:1], nPCLKB
Test Conditions
V
CC
= V
IN
V
CC
= V
IN
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-200
-200
0.15
1.2
V
CC
– 1.125
V
CC
– 1.895
0.6
V
CC
– 1.005
V
CC
– 1.78
1.2
V
CC
V
CC
– 0.875
V
CC
– 1.62
1.0
Minimum
Typical
Maximum
200
200
Units
μA
μA
μA
μA
V
V
V
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Output High Current; NOTE 3
Output Low Current; NOTE 3
Peak-to-Peak Output Voltage Swing
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
NOTE 3: Outputs terminated with 50 to V
CC
– 2V.
AC Electrical Characteristics
Table 5. AC Characteristics, V
CC
= 2.375V to 3.465V, V
EE
= 0V or V
CC
= 0V, V
EE
= -3.465V to -2.375V, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tsk(pp)
tjit
MUX_
ISOLATION
t
R
/ t
F
Parameter
Output Frequency
Propagation Delay;
NOTE 1
QA, nQA
QBx, nQBx
225
195
335
305
Test Conditions
Minimum
Typical
Maximum
2.5
445
420
200
622.08MHz Integration
Range: 12kHz - 20MHz
ƒ
OUT
= 622.08MHz,
V
PP
= 800mV
20% to 80%
75
0.035
65
155
250
Units
GHz
ps
ps
ps
ps
dB
ps
Part-to-Part Skew; NOTE 2, 3
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section; NOTE 4
MUX Isolation; NOTE 5
Output Rise/Fall Time
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters are measured
1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Measured using clock input at 622.08MHz.
NOTE 5: Q/nQ output measured differentially. See
Parameter Measurement Information
for MUX Isolation diagram.
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©2017 Integrated Device Technology, Inc.
ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz band
at a specified offset from the fundamental frequency to the power
value of the fundamental. This ratio is expressed in decibels (dBm)
or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a
dBc
value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 0.035ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator”.
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©2017 Integrated Device Technology, Inc.
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