INTEGRATED CIRCUITS
74ABT377A
Octal D-type flip-flop with enable
Product specification
Replaces data sheet 74ABT377 of 1995 Sep 06
IC23 Data Handbook
1997 Feb 26
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74ABT377A
FEATURES
•
Ideal for addressable register applications
•
8-bit positive edge-triggered register
•
Enable for address and data synchronization applications
•
Output capability: +64mA/-32mA
•
Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT377A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT377A has 8 edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered clock (CP)
input loads all flip-flops simultaneously when the Enable (E) input is
Low.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The E input must be stable one setup time prior to the Low-to-High
clock transition for predictable operation.
•
Power-up reset
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
I
CCH
PARAMETER
Propagation delay
CP to Qn
Input capacitance
Total current supply
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs High; V
CC
= 5.5V
TYPICAL
3.1
3.6
4
500
UNIT
ns
pF
nA
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIP
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT377A N
74ABT377A D
74ABT377A DB
74ABT377A PW
NORTH AMERICA
74ABT377A N
74ABT377A D
74ABT377A DB
74ABT377PWA DH
DWG NUMBER
SOT146-1
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
LOGIC SYMBOL
E
Q0
1
2
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
2
5
6
9
12
15
16
19
11
D0
CP
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
D0 3
D1 4
Q1
Q2
5
6
1
OE
Q0 Q1 Q2 Q3
Q4 Q5 Q6 Q7
D2 7
D3 8
Q3
9
GND 10
SA00155
SA00152
1997 Feb 26
2
853-1457 17800
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74ABT377A
LOGIC SYMBOL (IEEE/IEC)
PIN DESCRIPTION
PIN NUMBER
1
SYMBOL
E
D0-D7
Q0-Q7
CP
GND
V
CC
FUNCTION
Enable input (active–Low)
Data inputs
Data outputs
Clock Pulse input (active
rising edge)
Ground (0V)
Positive supply voltage
1
11
G1
IC2
3, 4, 7, 8, 13, 14,
17, 18
2, 5, 6, 9, 12, 15,
16, 19
3
4
7
8
13
14
17
18
2D
2
11
5
6
9
12
15
16
19
10
20
SA00157
LOGIC DIAGRAM
D0
3
1
E
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
CP
11
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
SA00158
1997 Feb 26
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74ABT377A
FUNCTION TABLE
INPUTS
E
l
l
CP
↑
↑
Dn
h
l
OUTPUTS
Qn
H
L
Load “1”
Load “0”
Hold (do nothing)
OPERATING MODE
H
h
L
l
X
↑
=
=
=
=
=
=
h
↑
X
no change
H
X
X
no change
High voltage level
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
Don’t care
Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
4.5
0
2.0
0.8
–32
64
5
+85
LIMITS
MAX
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
1997 Feb 26
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74ABT377A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
MIN
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
OH
High–level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
OL
V
RST
I
I
I
OFF
I
CEX
I
O
I
CCH
I
CCL
∆I
CC
Additional supply current per
input pin
2
Low-level output voltage
Power-up output low
voltage
3
Input leakage current
Power-off leakage current
Output High leakage current
Output current
1
Quiescent supply current
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
–50
2.5
3.0
2.0
TYP
–0.9
2.9
3.4
2.4
0.42
0.13
±0.01
±5.0
5.0
–100
0.5
24
0.5
0.55
0.55
±1.0
±100
50
–180
250
30
1.5
–50
MAX
–1.2
2.5
3.0
2.0
0.55
0.55
±1.0
±100
50
–180
250
30
1.5
T
amb
= –40°C
to +85°C
MIN
MAX
–1.2
V
V
V
V
V
V
µA
µA
µA
mA
µA
mA
mA
UNIT
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
1
SYMBOL
PARAMETER
WAVEFORM
MIN
f
MAX
Maximum clock frequency
1
1
150
1.8
2.2
T
amb
= +25
o
C
V
CC
= +5.0V
TYP
250
3.1
3.6
4.0
4.7
MAX
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V +0.5V
MIN
150
1.8
2.2
4.8
4.9
MAX
MHz
ns
UNIT
t
PLH
Propagation delay
t
PHL
CP to Qn
NOTE:
1. Limits may vary among suppliers.
1997 Feb 26
5
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