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74LVC541A
Octal buffer/line driver with 5 V tolerant inputs/outputs;
3-state
Rev. 4 — 25 November 2011
Product data sheet
1. General description
The 74LVC541A is an octal non-inverting buffer/line driver with 5 V tolerant inputs and
outputs. The 3-state outputs are controlled by the output enable inputs OE1 and OE2.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs for interlacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC541A
Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC541AD
74LVC541ADB
74LVC541APW
74LVC541ABQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO20
SSOP20
TSSOP20
DHVQFN20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
Type number
plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
4. Functional diagram
2
A0
Y0
18
3
1
19
2
3
4
5
6
7
8
9
mna898
A1
Y1
17
&
EN
18
4
A2
Y2
16
5
17
16
15
14
13
12
11
8
7
6
A3
Y3
15
A4
Y4
14
A5
Y5
13
A6
Y6
12
9
A7
Y7
11
OE1
1
19
OE2
mna900
Fig 1. IEC logic symbol
Fig 2. Functional diagram
74LVC541A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 25 November 2011
2 of 17
NXP Semiconductors
74LVC541A
Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
74LVC541A
OE1
2
3
4
5
6
7
8
9
GND 10
Y7 11
GND
(1)
1
A0
A1
terminal 1
index area
20 V
CC
19
OE2
18
Y0
17
Y1
16
Y2
15
Y3
14
Y4
13
Y5
12
Y6
OE1
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 V
CC
19 OE2
18 Y0
17 Y1
16 Y2
15 Y3
14 Y4
13 Y5
12 Y6
11 Y7
001aad115
A2
A3
A4
A5
A6
A7
74LVC541A
GND 10
001aad116
Transparent top view
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to GND.
Fig 3. Pin configuration for SO20 and (T)SSOP20
Fig 4. Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE1
A[0:7]
GND
Y[0:7]
OE2
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
output enable input (active LOW)
data input
ground (0 V)
bus output
output enable input (active LOW)
supply voltage
74LVC541A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 25 November 2011
3 of 17
NXP Semiconductors
74LVC541A
Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state
6. Functional description
Table 3.
Input
OE1
L
L
X
H
[1]
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high-impedance OFF-state
Functional table
[1]
Output
OE2
L
L
H
X
An
L
H
X
X
Yn
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+5.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
output 3-state or power-down
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
60
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
74LVC541A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 25 November 2011
4 of 17
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