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74LVC257A
Quad 2-input multiplexer with 5 V tolerant inputs/outputs;
3-state
Rev. 6 — 28 November 2011
Product data sheet
1. General description
The 74LVC257A is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of
data from two sources and are controlled by a common data select input (pin S). The data
inputs from source 0 (pins 1I0 to 4I0) are selected when pin S is LOW and the data inputs
from source 1 (pins 1I1 to 4I1) are selected when pin S is HIGH. Data appears at the
outputs (pins 1Y to 4Y) in true (non-inverting) form from the selected inputs. The device is
the logic implementation of a 4-pole, 2-position switch, where the position of the switch is
determined by the logic levels applied to pin S. The outputs are forced to a
high-impedance OFF-state when pin OE is HIGH.
Inputs can be driven from either 3.3 V or 5.0 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Output drive capability 50
transmission lines at 85
C
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC257A
Quad 2-input multiplexer with 5V tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC257AD
74LVC257ADB
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
74LVC257APW
40 C
to +125
C
74LVC257ABQ
40 C
to +125
C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
1
2
3
5
6
11
10
14
13
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
S
1
OE
mna865
G1
EN
15
1Y
2Y
3Y
4Y
2
4
7
9
12
3
5
1
1
MUX
4
7
6
11
9
10
14
12
13
mna866
15
Fig 1.
Logic diagram
Fig 2.
IEC logic symbol
74LVC257A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 28 November 2011
2 of 18
NXP Semiconductors
74LVC257A
Quad 2-input multiplexer with 5V tolerant; 3-state
1I1
1Y
1I0
2I1
2Y
2I0
2
3
5
6
11
10
14
13
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
SELECTOR
3-STATE
MULTI-
PLEXER
OUTPUTS
2Y
7
3I0
3Y
9
4I1
4Y
4Y 12
4I0
1Y
4
3I1
3Y
1 S
15 OE
OE
S
mna868
mna867
Fig 3.
Functional diagram
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
74LVC257A
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
1
2
3
4
5
6
7
8
001aad097
16 V
CC
15 OE
14 4I0
13 4I1
12 4Y
11 3I0
10 3I1
terminal 1
index area
1I0
1I1
1Y
2I0
2I1
2Y
2
3
4
5
6
7
16 V
CC
15 OE
14 4I0
13 4I1
12 4Y
11 3I0
10 3I1
3Y
9
GND
(1)
8
GND
1
S
257A
9
3Y
001aad098
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration for SO24 and (T)SSOP24
Fig 6.
Pin configuration for DHVQFN24
74LVC257A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 28 November 2011
3 of 18
NXP Semiconductors
74LVC257A
Quad 2-input multiplexer with 5V tolerant; 3-state
5.2 Pin description
Table 2.
Symbol
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
3Y
3I1
3I0
4Y
4I1
4I0
OE
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
common data select input
data input from source 0
data input from source 1
3-state multiplexer output
data input from source 0
data input from source 1
3-state multiplexer output
ground (0 V)
3-state multiplexer output
data input from source 1
data input from source 0
3-state multiplexer output
data input from source 1
data input from source 0
3-state output enable input (active LOW)
supply voltage
6. Functional description
Table 3.
Input
OE
H
L
L
L
L
[1]
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high-impedance OFF-state
Function table
[1]
Output
S
X
H
H
L
L
nI0
X
X
X
L
H
nI1
X
L
H
X
X
nY
Z
L
H
L
H
74LVC257A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 28 November 2011
4 of 18
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