FemtoClock
®
Crystal-to-LVDS Frequency
Synthesizer w/Integrated Fanout Buffer
ICS844256D
DATA SHEET
General Description
The ICS844256D is a Crystal-to-LVDS Clock Synthesizer/Fanout
Buffer designed for SONET and Gigabit Ethernet applications. The
output frequency can be set using the frequency select pins and a
25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal for
SONET. The low phase noise characteristics of the ICS844256D
make it an ideal clock for these demanding applications.
Features
•
•
•
•
•
•
•
•
Six differential LVDS output pairs
Crystal oscillator interface
Output frequency range: 62.5MHz - 625MHz
Crystal input frequency range:15.625MHz - 25.5MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.43ps (typical)
Full 3.3V or mixed 3.3V core, 2.5V output supply mode
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Function
Divider Function Table
Inputs
FB_SEL
0
0
0
0
1
1
1
1
N_SEL1
0
0
1
1
0
0
1
1
N_SEL0
0
1
0
1
0
1
0
1
M Divider Value
25
25
25
25 (default)
32
32
32
32
N Divider Value
1
2
4
5
1
2
4
8
M/N Divider Value
25
12.5
6.25
5
32
16
8
4
Block Diagram
Q0
PLL_BYPASS
Pullup
nQ0
Q1
1
Pin Assignment
V
DDO
V
DDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
PLL_BYPASS
V
DDA
V
DD
FB_SEL
XTAL_IN
OSC
XTAL_OUT
PLL
0
N
Output
Divider
nQ1
Q2
nQ2
Q3
M
Feedback
Divider
FB_SEL
Pulldown
N_SEL1
Pullup
nQ3
Q4
nQ4
Q5
nQ5
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q3
nQ3
Q4
nQ4
Q5
nQ5
N_SEL1
GND
GND
N_SEL0
XTAL_OUT
XTAL_IN
ICS844256D
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
N_SEL0
Pullup
ICS844256DG REVISION A AUGUST 5, 2010
1
©2010 Integrated Device Technology, Inc.
ICS844256D Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 8
9
10
11
12
13,
14
15,
18
16, 17
19, 20
21, 22
23, 24
Name
V
DDO
nQ2, Q2
nQ1, Q1
nQ0, Q0
PLL_BYPASS
V
DDA
V
DD
FB_SEL
XTAL_IN,
XTAL_OUT
N_SEL0,
N_SEL1
GND
nQ5, Q5
nQ4, Q4
nQ3, Q3
Power
Output
Output
Output
Input
Power
Power
Input
Input
Input
Power
Output
Output
Output
Pullup
Pulldown
Pullup
Type
Description
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH,
the PLL is bypassed and the output frequency = crystal frequency ÷ N output
divider. LVCMOS / LVTTL interface levels.
Analog supply pin.
Core supply pin.
Feedback and output frequency select pin. LVCMOS/LVTTL interface levels.
See Table 3.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Feedback and output frequency select pins. LVCMOS/LVTTL interface levels.
See Table 3.
Power supply ground.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS844256DG REVISION A AUGUST 5, 2010
2
©2010 Integrated Device Technology, Inc.
ICS844256D Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Function Tables
Table 3. Example Frequency Function Table
Inputs
XTAL (MHz)
20
20
20
20
21.25
24
24
24
24
25
25
25
25
25.5
15.625
18.5625
18.75
18.75
18.75
18.75
19.44
19.44
19.44
19.44
19.53125
19.53125
19.53125
19.53125
20
FB_SEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N_SEL1
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
N_SEL0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
M Divider Value
25
25
25
25
25
25
25
25
25
25
25
25
25
25
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Function
VCO (MHz)
500
500
500
500
531.25
600
600
600
600
625
625
625
625
637.5
500
594
600
600
600
600
622.08
622.08
622.08
622.08
625
625
625
625
640
N Divider Value
1
2
4
5
5
1
2
4
5
1
2
4
5
4
8
8
1
2
4
8
1
2
4
8
1
2
4
8
8
Output (MHz)
500
250
125
100
106.25
600
300
150
120
625
312.5
156.25
125
159.375
62.5
74.25
600
300
150
75
622.08
311.04
155.52
77.76
625
312.5
156.25
78.125
80
ICS844256DG REVISION A AUGUST 5, 2010
3
©2010 Integrated Device Technology, Inc.
ICS844256D Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
10mA
15mA
32.1°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.11
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
172
11
72
Units
V
V
V
mA
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.11
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
2.625
172
11
70
Units
V
V
V
mA
mA
mA
ICS844256DG REVISION A AUGUST 5, 2010
4
©2010 Integrated Device Technology, Inc.
ICS844256D Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
FB_SEL
Input High Current
PLL_BYPASS,
N_SEL0, N_SEL1
FB_SEL
I
IL
Input Low Current
PLL_BYPASS,
N_SEL0, N_SEL1
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
Table 4D. LVDS DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
1.25
Test Conditions
Minimum
247
Typical
350
Maximum
454
50
1.45
50
Units
mV
mV
V
mV
Table 4E. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
1.25
Test Conditions
Minimum
247
Typical
350
Maximum
454
50
1.45
50
Units
mV
mV
V
mV
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
15.625
Test Conditions
Minimum
Typical
Fundamental
25.5
50
7
1
MHz
Maximum
Units
Ω
pF
mW
ICS844256DG REVISION A AUGUST 5, 2010
5
©2010 Integrated Device Technology, Inc.
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