NVT4556
SIM card interface level translator with I
2
C-bus control and
LDO
Rev. 1.1 — 25 August 2015
Product data sheet
1. General description
The NVT4556 device is built for interfacing a SIM card with a single low-voltage host-side
interface. The NVT4556 contains an LDO that can deliver two different voltages, 1.8 V or
3 V, from a typical mobile phone battery voltage, and three level translators to convert the
data, RSTn and CLKn signals between a SIM card and a host microcontroller.
The NVT4556 V
CC
pin provides power to the host side I/Os and doubles as an enable pin,
for this reason it can be connected to a GPIO that matches the host side voltage. The total
current draw from the V
CC
pin is only 100
A
maximum. The NVT4556 also uses the
I
2
C-bus interface to enable normal operation and to select either 1.8 V or 3 V for the SIM
card power supply. The NVT4556 can also disable the LDO functionality while maintaining
the level translator paths so that the user can use a system-controlled regulator to power
the SIM card power supply. The NVT4556 can enable users to provide second and third
SIM card functionality with a low-voltage one host SIM port, at the same time reducing the
number of GPIOs used in the system. The NVT4556 is compliant with all ETSI, IMT-2000
and ISO-7816 SIM/Smart card interface requirements.
The NVT4556 is available in a 12-pin WLCSP package and has three factory
programmed slave address options.
2. Features and benefits
Support SIM card supply voltages 1.8 V and 3 V
Input voltage range to LDO: 2.5 V to 5.25 V
Host microcontroller operating voltage range: 1.55 V to 3.6 V
V
CC
input pin provides both host supply voltage and logic level hardware
enable/disable pin: source through Host GPIO (I
CC
<100
A)
RST_HOST/EN pin can be programmed as a reset pin or as a device enable/disable
pin
Level translation of I/O, RSTn and CLKn between SIM card and host-side interface
with capacitive isolation
I
2
C-bus interface for device enable and LDO voltage selection
Low current shutdown mode < 3
A
Supports clock speed beyond 5 MHz clock
Supports CLK stop mode
Integrated EMI filters
Incorporates ISO-7816-3 shutdown feature for the SIM card signals
ETSI, IMT2000 and ISO-7816 compliant
8
kV IEC61000-4-2 ESD protected on all SIM card contact pins
NXP Semiconductors
NVT4556
SIM card interface level translator with I
2
C-bus control and LDO
Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen
and antimony (Dark Green compliant)
Available in 12-pin WLCSP package (1.205 mm
1.605 mm
0.412 mm,
0.4 mm pitch)
3. Applications
NVT4556 can be used with a range of SIM card attached devices including:
Mobile and personal phones
Wireless modems
SIM card terminals
4. Ordering information
Table 1.
Ordering information
Topside
mark
556A
556B
Package
Name
WLCSP12
WLCSP12
Description
wafer level chip-size package; 12 balls;
body 1.205
1.605
0.412 mm (Backside coating included)
wafer level chip-size package; 12 balls;
body 1.205
1.605
0.412 mm (Backside coating included)
Version
NVT4556AUK
NVT4556BUK
Type number
NVT4556AUK
NVT4556BUK
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
NVT4556AUKZ
Package
Packing method
Minimum Temperature
order
quantity
3000
T
amb
=
40 C
to +85
C
Slave
address
1100 000xb
Type number
NVT4556AUK
WLCSP12 Reel 7” Q1/T1
*Special mark chips
dry pack
WLCSP12 Reel 7” Q1/T1
*Special mark chips
dry pack
NVT4556BUK
NVT4556BUKZ
3000
T
amb
=
40 C
to +85
C
1100 001xb
NVT4556
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 25 August 2015
2 of 27
NXP Semiconductors
NVT4556
SIM card interface level translator with I
2
C-bus control and LDO
5. Functional diagram
SDA
I
2
C-BUS
SCL
V
BAT
LDO
REGISTERS
AND
CONTROL LOGIC
VSIM
V
CC
RST_HOST/EN
UVLO
RST_SIM
CLK_HOST
CLK_SIM
IO_HOST
IO_SIM
GND
002aah626
Fig 1.
Functional diagram
6. Pinning information
bump A1
index area
NVT4556UK
A1
A2
A3
B1
B2
B3
A
1
IO_HOST
RST_HOST/
EN
CLK_HOST
CLK_SIM
2
GND
SDA
SCL
RST_SIM
3
V
CC
V
BAT
VSIM
IO_SIM
002aah627
C1
C2
C3
B
C
D1
D2
D3
002aah634
D
Transparent top view
Transparent top view
Fig 2.
Bump configuration for WLCSP12
Fig 3.
Bump mapping for WLCPS12
NVT4556
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 25 August 2015
3 of 27
NXP Semiconductors
NVT4556
SIM card interface level translator with I
2
C-bus control and LDO
6.1 Pin description
Table 3.
Symbol
IO_HOST
GND
V
CC
Pin description
Pin
A1
A2
A3
Type
I/O
ground
power
Description
Host controller bidirectional data input/output. This output
must be on an open-drain configuration.
Ground for the SIM card and host controller. Proper grounding
and bypassing are required to meet ESD specifications.
Supply voltage for the host controller side input/output pins
(CLK_HOST, RST_HOST/EN, IO_HOST). When V
CC
is below
the UVLO threshold, the VSIM supply is disabled. This pin
should be bypassed with a 100 nF ceramic capacitor close to
the pin.
Reset input from host controller or acts as a programmable
logic-level enable/disable when bit 6 = 1.
Digital input/output. I
2
C-bus serial bidirectional data line;
open-drain.
Battery voltage supply for internal LDO. This input voltage
ranges from 2.5 V to 5.25 V. This pin should be bypassed with
a 1.0
F
ceramic capacitor close to the pin.
Clock input from host controller.
Digital input. I
2
C-bus serial bidirectional clock line.
SIM card supply voltage from internal LDO. The voltage at this
pin can be selected for either 1.8 V (CTRL = 0) or 3 V
(CTRL = 1). This pin should be bypassed with a 4.7
F
ceramic capacitor close to the pin.
Clock output pin for the SIM card.
Reset output pin for the SIM card.
SIM card bidirectional data input/output. The SIM card output
must be on an open-drain driver.
RST_HOST/EN
SDA
V
BAT
B1
B2
B3
I
I/O
power
CLK_HOST
SCL
VSIM
C1
C2
C3
I
I
power
CLK_SIM
RST_SIM
IO_SIM
D1
D2
D3
O
O
I/O
NVT4556
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 25 August 2015
4 of 27
NXP Semiconductors
NVT4556
SIM card interface level translator with I
2
C-bus control and LDO
7. Functional description
Refer to
Figure 1 “Functional diagram”.
7.1 Shutdown sequence of NVT4556
The ISO 7816-3 specification specifies the shutdown sequence for the SIM card signals.
This shutdown sequence ensures that these channels are properly disabled and does not
have any accidental corruption of data. Also during hot swap, the orderly shutdown of
these signals helps to avoid any improper write and corruption of data.
When the V
CC
falls below its UVLO threshold, a shutdown sequence is immediately
initiated. The RST_SIM is first driven LOW after a short delay the CLK_SIM and IO_SIM
are driven LOW followed by VSIM. An internal pull-down resistor on the SIM pins is used
to pull these channels LOW. The shutdown sequence is completed in a few
microseconds.
UVLO
threshold
V
CC
RST_SIM
t
dis(CLK_SIM)
CLK_SIM
IO_SIM
ACTIVE DATA
t
dis(VSIM)
VSIM
002aah639
Fig 4.
V
CC
UVLO shutdown sequence for RST_SIM, CLK_SIM, IO_SIM and VSIM of
NVT4556 SIM card translator
The shutdown sequence can also be initiated by one of two events: by de-asserting the
RST_HOST/EN pin if bit 6 (RST_HOST pin mode select bit) is set to 1, or by writing a 0 to
bit 0 (Device enable bit) if bit 6 is set to 0. The shutdown sequence consists of first
powering down the RST_SIM channel. Once the RST_SIM channel is powered down,
CLK_SIM, IO_SIM and VSIM are powered down sequentially one-by-one. An internal
pull-down resistor on the SIM pins is used to pull these channels LOW. The shutdown
sequence is completed in a few microseconds. It is important that enable is written LOW
before V
BAT
and V
CC
supplies go LOW to ensure that the shutdown sequence is properly
initiated. The NVT4556 is enabled and disabled at the end of the I
2
C-bus write sequence,
so a delay in the start of the I/O signals should account for time of this data sequence.
NVT4556
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 25 August 2015
5 of 27
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