CYRF69103
Programmable Radio-on-Chip Low Power
Programmable Radio on Chip Low Power
PRoC™ LP Features
■
Single Device, Two Functions
❐
8-bit Flash based MCU function and 2.4 GHz radio
transceiver function in a single device.
Flash Based Microcontroller Function
❐
M8C based 8-bit CPU, optimized for Human Interface
Devices (HID) applications
❐
256 Bytes of SRAM
❐
8 Kbytes of Flash memory with EEPROM emulation
❐
In-System reprogrammable
❐
CPU speed up to 12 MHz
❐
16-bit free running timer
❐
Low power wakeup timer
❐
12-bit Programmable Interval Timer with interrupts
❐
Watchdog timer
Industry leading 2.4 GHz Radio Transceiver Function
❐
Operates in the unlicensed worldwide Industrial, Scientific,
and Medical (ISM) band (2.4 GHz to 2.483 GHz)
❐
DSSS data rates of up to 250 Kbps
❐
GFSK data rate of 1 Mbps
❐
–97 dBm receive sensitivity
❐
Programmable output power up to +4 dBm
❐
Auto Transaction Sequencer (ATS)
❐
Framing CRC and Auto ACK
❐
Received Signal Strength Indication (RSSI)
❐
Automatic Gain Control (AGC)
Component Reduction
❐
Integrated 1.8 V boost converter
❐
GPIOs that require no external components
❐
Operates off a single crystal
Flexible I/O
❐
2 mA source current on all GPIO pins. Configurable 8 mA or
50 mA/pin current sink on designated pins
Each GPIO pin supports high impedance inputs, configurable
pull up, open drain output, CMOS/TTL inputs, and CMOS
output
❐
Maskable interrupts on all I/O pins
❐
■
■
■
■
Operating Voltage from 1.8 V to 3.6 V DC
Operating Temperature from 0 to 70 °C
Pb-free 40-pin QFN Package
Advanced Development Tools based on Cypress’s PSoC
®
Tools
■
Applications
The CYRF69103 PRoC LP is targeted for the following
applications:
■
■
Wireless HID devices:
❐
Mice
❐
Remote Controls
❐
Presenter tools
❐
Barcode scanners
❐
POS terminal
General purpose wireless applications:
❐
Industrial applications
❐
Home automation
❐
White goods
❐
Consumer electronics
❐
Toys
■
■
Functional Description
PRoC LP devices are integrated radio and microcontroller
functions in the same package to provide a dual-role single-chip
solution.
Communication between the microcontroller and the radio is
through the radio’s SPI interface.
■
Cypress Semiconductor Corporation
Document Number: 001-07611 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 19, 2017
Not recommended for new designs
CYRF69103
Logic Block Diagram
47µF
MOSI
SCK
nSS
V
CC
470nF
V
CC
10 µF
V
Bat1
V
Bat0
L/D
V
DD_MICRO
RST
V
Bat2
V
Reg
V
CC1
V
CC2
V
CC3
V
IO
RFbias
RFp
RFn
Microcontroller
Function
P0_1,3,4,7
4
P1_0:2,6:7
5
P2_0:1
GND
2
P1.5/MOSI
P1.4/SCK
P1.3/nSS
Radio
Function
IRQ/GPIO
MISO/GPIO
XOUT/GPIO
PACTL/GPIO
RESV
GND
Vdd
Xtal
.....
12 MHz
.......
470 nF
Document Number: 001-07611 Rev. *J
Page 2 of 72
Not recommended for new designs
GND
CYRF69103
Contents
Functional Overview ........................................................ 4
2.4 GHz Radio Function .............................................. 4
Data Transmission Modes ........................................... 4
Microcontroller Function .............................................. 4
Backward Compatibility ............................................... 4
DDR Mode ................................................................... 5
SDR Mode .................................................................. 5
Pinouts .............................................................................. 6
Pin Definitions .................................................................. 6
Functional Block Overview .............................................. 7
2.4 GHz Radio ............................................................. 7
Frequency Synthesizer ................................................ 7
Baseband and Framer ................................................. 7
Packet Buffers and Radio Configuration Registers ..... 8
Auto Transaction Sequencer (ATS) ............................ 8
Interrupts ..................................................................... 9
Clocks .......................................................................... 9
GPIO Interface ............................................................ 9
Power On Reset/Low Voltage Detect .......................... 9
Timers ......................................................................... 9
Power Management .................................................... 9
Low Noise Amplifier (LNA)
and Received Signal Strength Indication (RSSI) .............. 11
Receive Spurious Response ..................................... 11
SPI Interface .................................................................... 11
3-Wire SPI Interface .................................................. 11
4-Wire SPI Interface .................................................. 11
SPI Communication and Transactions ...................... 12
SPI I/O Voltage References ...................................... 12
SPI Connects to External Devices ............................ 12
CPU Architecture ............................................................ 13
CPU Registers ................................................................. 14
Flags Register ........................................................... 14
Accumulator Register ................................................ 14
Index Register ........................................................... 15
Stack Pointer Register ............................................... 15
CPU Program Counter High Register ....................... 15
CPU Program Counter Low Register ........................ 15
Addressing Modes ......................................................... 16
Source Immediate ..................................................... 16
Source Direct ............................................................. 16
Source Indexed ......................................................... 16
Destination Direct ...................................................... 16
Destination Indexed ................................................... 17
Destination Direct Source Immediate ........................ 17
Destination Indexed Source Immediate .................... 17
Destination Direct Source Direct ............................... 17
Source Indirect Post Increment ................................. 18
Destination Indirect Post Increment .......................... 18
Instruction Set Summary ............................................... 19
Memory Organization ..................................................... 20
Flash Program Memory Organization ....................... 20
Data Memory Organization ....................................... 21
Flash .......................................................................... 21
SROM ........................................................................ 21
SROM Function Descriptions .................................... 22
Clocking .......................................................................... 25
SROM Table Read Description ................................. 26
Clock Architecture Description .................................. 27
CPU Clock During Sleep Mode ................................. 31
Reset ................................................................................ 32
Power On Reset ........................................................ 33
Watchdog Timer Reset .............................................. 33
Sleep Mode ...................................................................... 33
Sleep Sequence ........................................................ 33
Low Power in Sleep Mode ......................................... 34
Wakeup Sequence .................................................... 34
Low Voltage Detect Control ........................................... 36
POR Compare State ................................................. 37
ECO Trim Register .................................................... 37
General Purpose I/O Ports ............................................. 38
Port Data Registers ................................................... 38
GPIO Port Configuration ........................................... 39
GPIO Configurations for Low Power Mode ............... 44
Serial Peripheral Interface (SPI) ................................ 45
SPI Data Register ...................................................... 46
SPI Configure Register .............................................. 46
SPI Interface Pins ...................................................... 48
Timer Registers .............................................................. 48
Registers ................................................................... 48
Interrupt Controller ......................................................... 51
Architectural Description ........................................... 51
Interrupt Processing .................................................. 52
Interrupt Latency ....................................................... 52
Interrupt Registers ..................................................... 52
Microcontroller Function Register Summary ............. 56
Radio Function Register Summary ............................... 58
Absolute Maximum Ratings .......................................... 59
DC Characteristics ......................................................... 59
AC Characteristics ......................................................... 61
RF Characteristics .......................................................... 65
Ordering Information ...................................................... 67
Ordering Code Definitions ......................................... 67
Package Handling ........................................................... 68
Package Diagrams .......................................................... 68
Acronyms ........................................................................ 70
Document Conventions ................................................. 70
Units of Measure ....................................................... 70
Document History Page ................................................. 71
Sales, Solutions, and Legal Information ...................... 72
Worldwide Sales and Design Support ....................... 72
Products .................................................................... 72
PSoC® Solutions ...................................................... 72
Cypress Developer Community ................................. 72
Technical Support ..................................................... 72
Document Number: 001-07611 Rev. *J
Page 3 of 72
Not recommended for new designs
CYRF69103
Functional Overview
The CYRF69103 is a complete Radio System-on-Chip device,
providing a complete RF system solution with a single device and
a few discrete components. The CYRF69103 is designed to
implement low cost wireless systems operating in the worldwide
2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band
(2.400 GHz to 2.4835 GHz).
Both 64-chip and 32-chip data PN codes are supported. The four
data transmission modes apply to the data after the Start of
Packet (SOP). In particular, the packet length, data and CRC are
all sent in the same mode.
Microcontroller Function
The MCU function is an 8-bit Flash-programmable
microcontroller. The instruction set is optimized specifically for
HID and a variety of other embedded applications.
2.4 GHz Radio Function
The SoC contains a 2.4 GHz 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer, DSSS baseband controller,
Received Signal Strength Indication (RSSI), and SPI interface
for data transfer and device configuration.
The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).
In
DSSS modes the
baseband
performs
DSSS
spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK)
the baseband performs Start of Frame (SOF), End of Frame
(EOF) detection, and CRC16 generation and checking. The
baseband may also be configured to automatically transmit
Acknowledge (ACK) handshake packets whenever a valid
packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates, except SDR, enabling the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems, which use high data rates at shorter distances and/or
in a low moderate interference environment, and change to lower
data rates at longer distances and/or in high interference
environments.
The radio meets
requirements:
■
In addition, the MCU function includes a Watchdog timer, a
vectored interrupt controller, a 16-bit Free Running Timer, and
12-bit Programmable Interrupt Timer.
The microcontroller has 15 GPIO pins grouped into multiple
ports. With the exception of the four radio function GPIOs, each
GPIO port supports high impedance inputs, configurable pull up,
open drain output, CMOS/TTL inputs and CMOS output. Up to
two pins support programmable drive strength of up to 50 mA.
Additionally, each I/O pin can be used to generate a GPIO
interrupt to the microcontroller. Each GPIO port has its own GPIO
interrupt vector with the exception of GPIO Port 0. GPIO Port 0
has two dedicated pins that have independent interrupt vectors
(P0.3–P0.4).
The microcontroller features an internal oscillator.
The PRoC LP includes a Watchdog timer, a vectored interrupt
controller, a 12-bit programmable interval timer with configurable
1 ms interrupt and a 16-bit free running timer.
In addition, the CYRF69103 IC has a Power Management Unit
(PMU), which enables direct connection of the device to any
battery voltage in the range 1.8 V to 3.6 V. The PMU conditions
the battery voltage to provide the supply voltages required by the
device and may supply external devices.
the
following
worldwide
regulatory
Europe:
❐
ETSI EN 301 489-1 V1.4.1
❐
ETSI EN 300 328-1 V1.3.1
North America:
❐
FCC CFR 47 Part 15
Japan:
❐
ARIB STD-T66
Backward Compatibility
The CYRF69103 IC is fully interoperable with the main modes of
the first generation Cypress radios namely the CYWUSB6934
-LS and CYWWUSB6935-LR devices. The 62.5 kbps mode is
supported by selecting 32 chip DDR mode. Similarly, the
15.675 kbps mode is supported by selecting 64 chip SDR mode
In this method, a suitably configured CYRF69103 IC device may
transmit data to or receive data from a first generation device, or
both. Backwards compatibility requires disabling the SOP,
length, and CRC16 fields.
This section provides the different configurations of the registers
and firmware that enable a new generation radio to communicate
with a first generation radio. There are two possible modes: SDR
and DDR mode (8-DR and GFSK modes are not present in the
first generation radio). The second generation radio must be
initialized using the RadioInitAPI of the LP radio driver and then
the following registers’ bits need to be configured to the given
Byte values. Essentially, the following deactivates the added
features of the second generation radio and takes it down to the
level of the first generation radio. The data format, data rates,
and the PN codes used are recognizable by the first generation
radio.
■
■
Data Transmission Modes
The radio supports four different data transmission modes:
■
■
■
■
In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS
In 8DR mode, 1 byte is encoded in each PN code symbol
transmitted
In DDR mode, 2 bits are encoded in each PN code symbol
transmitted
In SDR mode, a single bit is encoded in each PN code symbol
transmitted
Document Number: 001-07611 Rev. *J
Page 4 of 72
Not recommended for new designs
The MCU function has up to 8 Kbytes of Flash for user’s code
and up to 256 bytes of RAM for stack space and user variables.
CYRF69103
DDR Mode
Table 1. DDR Mode
Register
TX_CFG_ADR
RX_CFG_ADR
Value
0X16
0X4B
32 chip PN Code, DDR, PA = 6
AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the device
uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is
enabled and the RX buffer is configured to receive eight bytes maximum.
Description
XACT_CFG_ADR
FRAMING_CFG_ADR
TX_OVERRIDE_ADR
RX_OVERRIDE_ADR
0X05
0X00
0X04
0X14
All SOP and framing features are disabled. Disable LEN_EN = 0 if EOP is needed.
Disable Transmit CRC-16.
The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled and
the receiver accepts bad packets that do not match the seed in CRC_seed registers. This
helps in communication with the first generation radio that does not have CRC capabilities.
Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the
slow channels in the first generation radio.
Sets the number of allowed corrupted bits to 3.
Sets the number of consecutive symbols for non-correlation to detect end of packet.
AAAA are the two preamble bytes. Any other byte can also be written into the preamble
register file. Recommended counts of the preamble bytes to be sent must be >4.
ANALOG_CTRL_ADR
DATA32_THOLD_ADR
EOP_CTRL_ADR
PREAMBLE_ADR
0X01
0X03
0x01
0xAAAA05
SDR Mode
Table 2. SDR Mode
Register
TX_CFG_ADR
RX_CFG_ADR
Value
0X3E
0X4B
64 chip PN code, SDR mode, PA = 6
AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the device
uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is
enabled and RX buffer is configured to receive eight bytes maximum. Enables RXOW to
allow new packets to be loaded into the receive buffer. This also enables the VALID bit
which is used by the first generation radio’s error correction firmware.
AutoACK is disabled. Forcing end state is disabled. The device is configured to transition
to Idle mode after Receive or Transmit. ACK timeout is set to 128 µs.
All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed.
Disable Transmit CRC-16.
The receiver rejects packets with a zero seed. The RX CRC-16 checker is disabled and
the receiver accepts bad packets that do not match the seed in the CRC_seed registers.
This helps in communication with the first generation radio that does not have CRC
capabilities.
Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the
slow channels in the first generation radio, for manual ACK consistency
Sets the number of allowed corrupted bits to 7 which is close to the recommended 12%
value.
Sets the number of consecutive symbols for non-correlation to detect end of packet.
AAAA are the two preamble bytes. Any other byte can also be written into the preamble
register file. Recommended counts of the preamble bytes to be sent must be >8.
Description
XACT_CFG_ADR
FRAMING_CFG_ADR
TX_OVERRIDE_ADR
RX_OVERRIDE_ADR
0X05
0X00
0X04
0X14
ANALOG_CTRL_ADR
DATA64_THOLD_ADR
EOP_CTRL_ADR
PREAMBLE_ADR
0X01
0X07
0xA1
0xAAAA09
Document Number: 001-07611 Rev. *J
Page 5 of 72
Not recommended for new designs
AutoACK is disabled. Forcing end state is disabled. The device is configured to transition
to Idle mode after a Receive or Transmit. ACK timeout is set to 128 µs.
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