DATASHEET
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBF32866B
design of the IDT74SSTUBF32866B must ensure that the
outputs will remain low, thus ensuring no glitches on the
output.
The device monitors both DCS and CSR inputs and will
gate the Qn outputs from changing states when both DCS
and CSR inputs are high. If either DCS and CSR input is
low, the Qn outputs will function normally. The RESET input
has priority over the DCS and CSR control and will force the
outputs low. If the DCS-control functionality is not desired,
then the CSR input can be hardwired to ground, in which
case, the setup-time requirement for DCS would be the
same as for the other D data inputs. Package options
include 96-ball LFBGA (MO-205CC).
Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is
designed for 1.7-V to 1.9-V V
DD
operation.
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized
to drive the DDR-II DIMM load. IDT74SSTUBF32866B
operates from a differential clock (CLK and CLK). Data are
registered at the crossing of CLK going high, and CLK
going low.
The C0 input controls the pinout configuration of the 1:2
pinout from A configuration (when low) to B configuration
(when high). The C1 input controls the pinout configuration
from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0,
C12 = 1)
Parity that arrives one cycle after the data input to which it
applies is checked on the PAR_IN of the first register. The
second register produces to PPO and QERR signals. The
QERR of the first register is left floating. The valid error
information is latched on the QERR output of the second
register. If an error occurs QERR is latched low for two
cycles or until RESET is low.
B - Single Configuration (C0 = 0, C1 = 0)
The device supports low-power standby operation. When
the RESET input (RESET) is low, the differential input
receivers are disabled, and undriven (floating) data, clock
and reference voltage (V
REF
) inputs are allowed. In
addition, when RESET is low all registers are reset, and all
outputs are forced low. The LVCMOS RESET and Cn inputs
must always be held at a valid logic high or low level. To
ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the low
state during power up.
In the DDR-II RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be
cleared and the outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. As long as the data inputs are low, and the clock
is stable during the time from the low-to-high transition of
RESET until the input receivers are fully enabled, the
Features
•
25-bit 1:1 or 14-bit 1:2 registered buffer with parity check
•
•
•
•
functionality
Supports SSTL_18 JEDEC specification on data inputs
and outputs
Supports LVCMOS switching levels on C0, C1, and
RESET inputs
Low voltage operation: V
DD
= 1.7V to 1.9V
Available in 96-ball LFBGA package
Applications
•
DDR2 Memory Modules
•
Provides complete DDR DIMM solution with
•
ICS98ULPA877A or IDTCSPUA877A
Ideal for DDR2 667 and 800
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
1
IDT74SSTUBF32866B
7067/13
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