Programmable System-on-Chip (PSoC )
General Description
PSoC
®
3: CY8C34 Family
Data Sheet
®
With its unique array of configurable blocks, PSoC
®
3 is a true system level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C34 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C34 family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C34 family isalso a high-performance configurable digital system with some
part numbers including interfaces such as USB, multimaster inter-integrated circuit (I
2
C), and controller area network (CAN). In
addition to communication interfaces, the CY8C34 family has an easy to configure logic array, flexible routing to all I/O pins, and a
high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt
components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C34 family provides
unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes
through simple firmware updates.
Features
Single cycle 8051 CPU core
DC to 50 MHz operation
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
Up to 8-KB flash error correcting code (ECC) or configuration
storage
Up to 8 KB SRAM
Up to 2 KB electrically erasable programmable read-only
memory (EEPROM), 1 M cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AHB
[1]
bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low-power
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5-V input through 1.8-V
to 5.0-V output
0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz
Low-power modes including:
• 1-µA sleep mode with real-time clock (RTC) and
low-voltage detect (LVD) interrupt
• 200-nA hibernate mode with RAM retention
Versatile I/O system
28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO),
two USBIOs
[2]
)
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46×16 segments
[2]
CapSense
®
support from any GPIO
[3]
1.2-V to 5.5-V I/O interface voltages, up to four domains
Maskable, independent interrupt request (IRQ) on any pin or
port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIOs configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
16 to 24 programmable logic device (PLD) based universal
digital blocks (UDB)
Full CAN 2.0b 16-receive (Rx), 8-transmit (Tx) buffers
[2]
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator
[2]
Up to four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), I
2
C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
Analog peripherals (1.71 V
≤
V
DDA
≤
5.5 V)
1.024 V±0.9-percent internal voltage reference across –40 °C
to +85 °C (14 ppm/°C)
Configurable delta-sigma ADC with 8- to12-bit resolution
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
Two 8-bit, 8-Msps IDACs or 1-Msps VDACs
Four comparators with 95-ns response time
Two uncommitted opamps with 25-mA drive capability
Two configurable multifunction analog blocks. Example
configurations are programmable gain amplifier (PGA),
transimpedance amplifier (TIA), mixer, and sample and hold
CapSense support
Programming, debug, and trace
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
Eight address and one data breakpoint
4-KB instruction trace buffer
Bootloader programming supportable through I
2
C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3- to 24-MHz internal oscillator over full temperature and
voltage range
4- to 25-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 50 MHz
32.768-kHz watch crystal oscillator
Low-power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40 °C to +85 °C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP
package options
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See
Ordering Information
on page 115 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation
Document Number: 001-53304 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 20, 2011
PSoC
®
3: CY8C34 Family
Data Sheet
Contents
1. Architectural Overview ..................................................... 3
2. Pinouts ............................................................................... 5
3. Pin Descriptions .............................................................. 10
4. CPU ................................................................................... 11
4.1 8051 CPU ................................................................. 11
4.2 Addressing Modes .................................................... 11
4.3 Instruction Set .......................................................... 12
4.4 DMA and PHUB ....................................................... 16
4.5 Interrupt Controller ................................................... 17
5. Memory ............................................................................. 21
5.1 Static RAM ............................................................... 21
5.2 Flash Program Memory ............................................ 21
5.3 Flash Security ........................................................... 21
5.4 EEPROM .................................................................. 21
5.5 Nonvolatile Latches (NVLs) ...................................... 22
5.6 External Memory Interface ....................................... 23
5.7 Memory Map ............................................................ 23
6. System Integration .......................................................... 25
6.1 Clocking System ....................................................... 25
6.2 Power System .......................................................... 28
6.3 Reset ........................................................................ 31
6.4 I/O System and Routing ........................................... 32
7. Digital Subsystem ........................................................... 38
7.1 Example Peripherals ................................................ 39
7.2 Universal Digital Block .............................................. 42
7.3 UDB Array Description ............................................. 45
7.4 DSI Routing Interface Description ............................ 46
7.5 CAN .......................................................................... 47
7.6 USB .......................................................................... 49
7.7 Timers, Counters, and PWMs .................................. 49
7.8 I
2
C ............................................................................ 49
8. Analog Subsystem .......................................................... 50
8.1 Analog Routing ......................................................... 52
8.2 Delta-sigma ADC ...................................................... 54
8.3 Comparators ............................................................. 55
8.4 Opamps .................................................................... 56
8.5 Programmable SC/CT Blocks .................................. 56
8.6 LCD Direct Drive ...................................................... 58
8.7 CapSense ................................................................. 59
8.8 Temp Sensor ............................................................ 59
8.9 DAC .......................................................................... 59
8.10 Up/Down Mixer ....................................................... 59
8.11 Sample and Hold .................................................... 60
9. Programming, Debug Interfaces, Resources ................ 60
9.1 JTAG Interface ......................................................... 61
9.2 Serial Wire Debug Interface ..................................... 62
9.3 Debug Features ........................................................ 63
9.4 Trace Features ......................................................... 63
9.5 Single Wire Viewer Interface .................................... 63
9.6 Programming Features ............................................. 63
9.7 Device Security ........................................................ 63
10. Development Support ................................................... 64
10.1 Documentation ....................................................... 64
10.2 Online ..................................................................... 64
10.3 Tools ....................................................................... 64
11. Electrical Specifications ............................................... 65
11.1 Absolute Maximum Ratings .................................... 65
11.2 Device Level Specifications .................................... 66
11.3 Power Regulators ................................................... 70
11.4 Inputs and Outputs ................................................. 74
11.5 Analog Peripherals ................................................. 82
11.6 Digital Peripherals .................................................. 99
11.7 Memory ................................................................ 102
11.8 PSoC System Resources ..................................... 108
11.9 Clocking ................................................................ 111
12. Ordering Information ................................................... 115
12.1 Part Numbering Conventions ............................... 116
13. Packaging ..................................................................... 117
14. Acronyms ..................................................................... 120
15. Reference Documents ................................................. 121
16. Document Conventions .............................................. 122
16.1 Units of Measure .................................................. 122
17. Revision History .......................................................... 123
18. Sales, Solutions, and Legal Information .................127
Document Number: 001-53304 Rev. *L
Page 2 of 127
PSoC
®
3: CY8C34 Family
Data Sheet
1. Architectural Overview
Introducing the CY8C34 family of ultra low-power, flash Programmable System-on-Chip (PSoC
®
) devices, part of a scalable
8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C34 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Digital Interconnect
SIO
GPIOs
Usage Example for UDB
Sequencer
4- 25 MHz
( Optional
)
System Wide
Resources
Xtal
Osc
Digital System
Universal Digital Block Array ( 24 x UDB)
8- Bit
Timer
UDB
Quadrature Decoder
UDB
16- Bit
PWM
UDB
16- Bit PRS
UDB
UDB
UDB
CAN
2.0
I2C
Master
/
Slave
22
Ω
UDB
UDB
8- Bit
Timer
Logic
UDB
UDB
UDB
UDB
I2C Slave
UDB
UDB
8- Bit SPI
12- Bit SPI
UDB
UDB
GPIOs
UDB
UDB
IMO
4x
Timer
Counter
PWM
FS USB
2.0
USB
PHY
Clock Tree
Logic
UDB
UART
UDB
UDB
12- Bit PWM
UDB
UDB
UDB
GPIOs
32. 68 KHz
7
( Optional
)
RTC
Timer
System Bus
WDT
and
Wake
GPIOs
Memory System
EEPROM
SRAM
CPU System
8051 or
Cortex M3
CPU
Interrupt
Controller
Program &
Debug
Program
Debug &
Trace
GPIOs
EMIF
ILO
Clocking System
FLASH
PHUB
DMA
Boundary
Scan
GPIOs
SIOs
Power Management
System
Analog System
LCD Direct
Drive
POR and
LVD
Sleep
Power
1.71 to
5.5V
1.8V LDO
SMP
2 x SC/ CT Blocks
(TIA, PGA, Mixer etc
)
ADC
+
2x
Opamp
-
3 per
Opamp
Del Sig
Temperature
Sensor
CapSense
ADC
2x DAC
4x
CMP
+
GPIOs
-
0. 5 to 5.5V
( Optional
)
Figure 1-1
illustrates the major components of the CY8C34
family. They are:
8051 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
Document Number: 001-53304 Rev. *L
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low-
power UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/PLD functionality,
together with a small state machine engine to support a wide
variety of peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
Page 3 of 127
PSoC
®
3: CY8C34 Family
Data Sheet
CY8C34 family these blocks can include four 16-bit timer,
counter, and PWM blocks; I
2
C slave, master, and multi-master;
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the
“Example
Peripherals”
section on page 39 of this data sheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
section on page 38 of this data sheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.9-percent
error over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Voltage references
Analog-to-digital converter (ADC)
Digital-to-analog converters (DACs)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±1 LSB
DNL less than ±1 LSB
SINAD better than 66 dB
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
Two high-speed voltage or current DACs support 8-bit output
signals at update rate of 8 Msps in current DAC (IDAC) and
1 Msps in voltage DAC (VDAC). They can be routed out of any
GPIO pin. You can create higher resolution voltage PWM DAC
outputs using the UDB array. This can be used to create a pulse
width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz.
The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADC and DACs, the analog subsystem
provides multiple:
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the
“Analog Subsystem”
section on page 50 of this data
sheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 50 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an error
correcting code (ECC) for high reliability applications. A powerful
and flexible protection model secures the user's sensitive
information, allowing selective memory block locking for read
and write protection. Up to 2 KB of byte-writeable EEPROM is
available on-chip to store application data. Additionally, selected
configuration options such as boot speed and pin drive mode are
stored in nonvolatile memory. This allows settings to activate
immediately after power-on reset (POR).
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the V
DDIO
pins. Every GPIO
has analog I/O, LCD drive
[4]
, CapSense
[5]
,
flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow V
OH
to be set independently of V
DDIO
when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I
2
C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with Full-Speed USB the USB
physical interface is also provided (USBIO). When not using
USB these pins may also be used for limited digital functionality
and device programming. All of the features of the PSoC I/Os are
covered in detail in the
“I/O System and Routing”
section on
page 32 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the master clock base for
the system, and has 1-percent accuracy at 3 MHz. The IMO can
be configured to run from 3 MHz up to 24 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs.
Notes
4. This feature on select devices only. See
Ordering Information
on page 115 for details.
5. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-53304 Rev. *L
Page 4 of 127
PSoC
®
3: CY8C34 Family
Data Sheet
The device provides a PLL to generate system clock frequencies
up to 50 MHz from the IMO, external crystal, or external
reference clock. It also contains a separate, very low-power
Internal low-speed oscillator (ILO) for the sleep and watchdog
timers. A 32.768-kHz external watch crystal is also supported for
use in RTC applications. The clocks, together with
programmable clock dividers, provide the flexibility to integrate
most timing requirements.
The CY8C34 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 V ± 5 percent, 2.5 V ±10 percent, 3.3 V ± 10 percent,
or 5.0 V ± 10 percent, or directly from a wide range of battery
types. In addition, it provides an integrated high efficiency
synchronous boost converter that can power the device from
supply voltages as low as 0.5 V. This enables the device to be
powered directly from a single battery or solar cell. In addition,
you can use the boost converter to generate other voltages
required by the device, such as a 3.3-V supply for LCD glass
drive. The boost’s output is available on the V
BOOST
pin, allowing
other devices in the application to be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
The details of the PSoC power modes are covered in the
“Power
System”
section on page 28 of this data sheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for ‘printf’ style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces enables you to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. PSoC supports on-chip break
points and 4 KB instruction and data race memory for debug.
Details of the programming, test, and debugging interfaces are
discussed in the
“Programming, Debug Interfaces, Resources”
section on page 60 of this data sheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in
Figure 2-1
through
Figure 2-4.
Using the Vddio pins, a single PSoC can
support multiple interface voltage levels, eliminating the need for
off-chip level shifters. Each Vddio may sink up to 100 mA total to
its associated I/O pins and opamps. On the 68-pin and 100-pin
devices each set of Vddio associated pins may sink up to 100
mA. The 48-pin device may sink up to 100 mA total for all Vddio0
plus Vddio2 associated I/O pins and 100 mA total for all Vddio1
plus Vddio3 associated I/O pins.
Figure 2-1. 48-pin SSOP Part Pinout
(SIO) P12[2]
(SIO) P12[3]
(OpAmp2out, GPIO) P0[0]
(OpAmp0out, GPIO) P0[1]
(OpAmp0+, GPIO) P0[2]
(OpAmp0-/Extref0, GPIO) P0[3]
Vddio0
(OpAmp2+, GPIO) P0[4]
(OpAmp2-, GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(IDAC2, GPIO) P0[7]
Vccd
Vssd
Vddd
(GPIO) P2[3]
(GPIO) P2[4]
Vddio2
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
Vssb
Ind
Vboost
Vbat
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
Vddio3
P15[1] (GPIO, MHz XTAL: Xi)
P15[0] (GPIO, MHz XTAL: Xo)
Vccd
Vssd
Vddd
[6]
P15[7] (USBIO, D-, SWDCK)
[6]
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
Vddio1
P1[5] (GPIO, nTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, configurable XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
Lines show
Vddio to I/O
supply
association
SSOP
Note
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-53304 Rev. *L
Page 5 of 127
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