74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
Rev. 02 — 15 November 2007
Product data sheet
1. General description
The 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74AHC86; 74AHCT86 provides a 2-input exclusive-OR function.
2. Features
s
s
s
s
s
s
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than V
CC
For 74AHC86 only: operates with CMOS input levels
For 74AHCT86 only: operates with TTL input levels
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101C exceeds 1000 V
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC86D
74AHCT86D
74AHC86PW
74AHCT86PW
74AHC86BQ
74AHCT86BQ
−40 °C
to +125
°C
DHVQFN14
−40 °C
to +125
°C
TSSOP14
−40 °C
to +125
°C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
4. Functional diagram
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
2Y
6
3Y
8
4Y
11
mna787
Fig 1. Logic symbol
1
2
=1
3
4
5
=1
6
9
10
A
Y
B
12
13
mna788
=1
8
=1
11
mna786
Fig 2. Logic diagram (one gate)
Fig 3. IEC logic symbol
74AHC_AHCT86_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 November 2007
2 of 14
NXP Semiconductors
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
5. Pinning information
5.1 Pinning
terminal 1
index area
1B
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aah083
2
3
4
5
6
7
GND
3Y
8
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
14 V
CC
13 4B
12 4A
1Y
2A
2B
2Y
74AHC86
74AHCT86
11 4Y
10 3B
9
8
3A
3Y
GND
(1)
1
1A
86
001aad105
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14, TSSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data outputs
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input nA
L
L
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Input nB
L
H
L
H
Output nY
L
H
H
L
74AHC_AHCT86_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 November 2007
3 of 14
NXP Semiconductors
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO14 package
TSSOP14 package
DHVQFN14 package
[1]
[2]
[3]
[4]
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
±20
±25
75
-
+150
500
500
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
mW
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
-
-
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Conditions
74AHC86
Min
2.0
0
0
−40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
74AHCT86
Min
4.5
0
0
−40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
°C
ns/V
ns/V
Unit
74AHC_AHCT86_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 November 2007
4 of 14
NXP Semiconductors
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
For type 74AHC86
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
−50 µA;
V
CC
= 2.0 V
I
O
=
−50 µA;
V
CC
= 3.0 V
I
O
=
−50 µA;
V
CC
= 4.5 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
I
O
=
−8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
µA;
V
CC
= 2.0 V
I
O
= 50
µA;
V
CC
= 3.0 V
I
O
= 50
µA;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
C
O
input leakage
current
V
I
= 5.5 V or GND; V
CC
= 0 V
to 5.5 V
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3.0
4.0
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
2.0
10
-
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.48
3.8
-
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
20
10
-
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.40
3.70
-
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
pF
pF
Conditions
Min
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
output
capacitance
HIGH-level
input voltage
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
For type 74AHCT86
V
IH
V
IL
V
OH
2.0
-
-
-
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
HIGH-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
=
−50 µA
I
O
=
−8.0
mA
LOW-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
= 50
µA
I
O
= 8.0 mA
4.4
3.94
-
-
4.5
-
0
-
-
-
0.1
0.36
4.4
3.8
-
-
-
-
0.1
0.44
4.4
3.70
-
-
-
-
0.1
0.55
V
V
V
V
V
OL
74AHC_AHCT86_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 November 2007
5 of 14
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