74LVT373
3.3 V octal D-type transparent latch; 3-state
Rev. 3 — 21 November 2011
Product data sheet
1. General description
The 74LVT373 is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The
two sections of the device are controlled independently by latch enable (LE) and output
enable (OE) control gates. The data on the Dn inputs are transferred to the latch outputs
when the latch enable (LE) input is HIGH. The latch remains transparent to the data inputs
while LE is HIGH, and stores the data that is present one setup time before the
HIGH-to-LOW enable transition.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors. The active-low output enable (OE) controls all eight
3-state buffers independent of the latch operation.
When OE is LOW, the latched or transparent data appears at the outputs. When OE is
HIGH, the outputs are in the high-impedance OFF-state, which means they will neither
drive nor load the bus.
The 74LVT373 is functionally identical to the 74LVT573, but has a different pin
arrangement.
2. Features and benefits
Inputs and outputs arranged for easy interfacing to microprocessors
3-state outputs for bus interfacing
Common output enable control
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up reset
Power-up 3-state
Latch-up protection
JESD78 class II exceeds 500 mA
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
NXP Semiconductors
74LVT373
3.3 V octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVT373D
74LVT373PW
40 C
to +85
C
40 C
to +85
C
Name
SO20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT360-1
Type number
4. Functional diagram
OE
LE
11
3
4
7
8
13
14
17
18
LE
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
001aae048
1
11
EN
C1
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
001aae049
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig 3.
74LVT373
Logic diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 21 November 2011
2 of 15
NXP Semiconductors
74LVT373
3.3 V octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
74LVT373
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
aaa-000410
GND 10
Fig 4.
Pin configuration for SO20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
D0 to D7
GND
LE
Q0 to Q7
V
CC
Pin description
Pin
1
3, 4, 7, 8, 13, 14, 17, 18
10
11
2, 5, 6, 9, 12, 15, 16, 19
20
Description
output enable input (active LOW)
data input
ground (0 V)
latch enable (active HIGH)
data output
supply voltage
6. Functional description
6.1 Function table
Table 3.
Function table
[1]
Control OE
L
L
L
H
Control LE
H
L
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
74LVT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Operating mode
Load and read register
enable
Latch and read register
Hold
Disable outputs
Input Dn
L
H
l
h
X
X
Dn
Internal register Output Qn
L
H
L
H
NC
NC
Dn
L
H
L
H
NC
Z
Z
Product data sheet
Rev. 3 — 21 November 2011
3 of 15
NXP Semiconductors
74LVT373
3.3 V octal D-type transparent latch; 3-state
= HIGH-to-LOW latch enable transition;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition;
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition;
Z = high-impedance OFF-state;
NC = no change;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
0.5
-
-
-
-
65
[2]
Max
+4.6
+7.0
+7.0
50
50
128
64
+150
150
500
Unit
V
V
V
mA
mA
mA
mA
C
C
mW
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
-
-
T
amb
=
40 C
to +85
C
[3]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
For SO20 packages: above 70
C
derate linearly with 8 mW/K.
For TSSOP20 packages: above 60
C
derate linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
current duty cycle
50 %; f
i
1 kHz
ambient temperature
input transition rise and fall rate
in free air
outputs enabled
Conditions
Min
2.7
0
2.0
-
-
-
-
40
-
Typ
-
-
-
-
-
-
-
-
-
Max
3.6
5.5
-
0.8
32
32
64
+85
10
Unit
V
V
V
V
mA
mA
mA
C
ns/V
74LVT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 21 November 2011
4 of 15
NXP Semiconductors
74LVT373
3.3 V octal D-type transparent latch; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IK
V
OH
input clamping voltage
HIGH-level output voltage
Conditions
V
CC
= 2.7 V; I
IK
=
18
mA
V
CC
= 2.7 V to 3.6 V;
I
OH
=
100 A
V
CC
= 2.7 V; I
OH
=
8
mA
V
CC
= 3.0 V; I
OH
=
32
mA
V
OL
LOW-level output voltage
V
CC
= 2.7 V; I
OL
= 100
A
V
CC
= 2.7 V; I
OL
= 24 mA
V
CC
= 3.0 V I
OL
= 16 mA
V
CC
= 3.0 V I
OL
= 32 mA
V
CC
= 3.0 V I
OL
= 64 mA
V
OL(pu)
I
I
power-up LOW-level
output voltage
input leakage current
V
CC
= 3.6 V; I
O
= 1 mA;
V
I
= GND or V
CC
all input pins;
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V
control pins;
V
CC
= 3.6 V; V
CC
or GND
data pins
V
CC
= 3.6 V; V
I
= V
CC
V
CC
= 3.6 V; V
I
= 0 V
I
OFF
I
BHL
I
BHH
I
BHHO
I
BHLO
I
LO
I
O(pu/pd)
I
OZ
power-off leakage current
bus hold LOW current
bus hold HIGH current
bus hold HIGH overdrive current
bus hold LOW overdrive current
output leakage current
power-up/power-down
output current
OFF-state output current
V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
Dn input; V
CC
= 3 V; V
I
= 0.8 V
Dn input; V
CC
= 3 V; V
I
= 2.0 V
Dn input; V
CC
= 3.6 V; V
I
= 0 V to
3.6 V
Dn input; V
CC
= 3.6 V; V
I
= 0 V to
3.6 V
Qn output HIGH when
V
O
= 5.5 V and V
CC
= 3.0 V
V
CC
1.2 V; V
O
= 0.5 V to V
CC
;
V
I
= GND or V
CC
; OE = don’t care
V
CC
= 3.6 V; V
I
= V
IH
or V
IL
output HIGH: V
O
= 3.0 V
output LOW: V
O
= 0.5 V
I
CC
supply current
V
CC
= 3.6 V; V
I
= GND or V
CC
;
I
O
= 0 A
outputs HIGH
outputs LOW
outputs disabled
[6]
[5]
[4]
[4]
[3]
[2]
T
amb
=
40 C
to +85
C
Min
1.2
Typ
[1]
0.9
Max
-
-
-
-
0.2
0.5
0.4
0.5
0.55
0.55
Unit
V
V
V
V
V
V
V
V
V
V
V
CC
0.2 V
CC
0.1
2.4
2.0
-
-
-
-
-
-
2.5
2.2
0.1
0.3
0.25
0.3
0.4
0.13
-
-
-
5
-
75
-
-
500
-
-
1
0.1
0.1
1
1
150
150
-
-
60
1
10
1
1
-
100
-
75
500
-
125
100
A
A
A
A
A
A
A
A
A
A
A
-
5
1
1
5
-
A
A
-
-
-
0.13
3
0.13
0.19
12
0.19
mA
mA
mA
74LVT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 21 November 2011
5 of 15
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