TOSHIBA Original CMOS 32-Bit Microcontroller
TLCS-900/H1 Series
TMP92CH21FG
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
TMP92CH21
CMOS 32-bit Microcontroller
TMP92CH21FG/JTMP92CH21
1.
Outline and Device Characteristics
The TMP92CH21 is a high-speed advanced 32-bit Microcontroller developed for controlling
equipment which processes mass data.
The TMP92CH21 has a high-performance CPU (900/H1 CPU) and various built-in I/Os.
The TMP92CH21FG is housed in a 144-pin flat package. The JTMP92CH21 is a chip form
product.
Device characteristics are as follows:
(1) CPU: 32-bit CPU (900/H1 CPU)
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Compatible with TLCS-900/L1 instruction code
16 Mbytes of linear address space
General-purpose register and register banks
Micro DMA: 8 channels (250 ns/4 bytes at f
SYS
= 20 MHz, best case)
(2) Minimum instruction execution time: 50 ns (at f
SYS
= 20 MHz)
(3) Internal memory
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Internal RAM: 16 Kbytes (can be used for program, data and display memory)
Internal ROM: 8 Kbytes (used as boot program)
Possible downloading of user program through either USB,
UART or NAND flash.
Expandable up to 512 Mbytes (shared program/data area)
Can simultaneously support 8,- 16- or 32-bit width external data bus
... dynamic data bus sizing
Separate bus system
Chip select output: 4 channels
(4) External memory expansion
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(5) Memory controller
(6) 8-bit timers: 4 channels
(7) 16-bit timer/event counter: 1 channel
(8) General-purpose serial interface: 2 channels
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UART/synchronous mode: 2 channels (channel 0 and 1)
IrDA ver.1.0 (115 kbps) mode selectable: 1 channel (channel 0)
92CH21-1
2009-06-19
TMP92CH21
(9) USB (universal serial bus) controller: 1 channel
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Compliant with USB ver.1.1
Full-speed (12 Mbps) (Low-speed is not supported.)
Endpoints spec
Endpoint 0: Control 64 bytes* 1-FIFO
Endpoint 1: BULK (out) 64 bytes* 2-FIFO
Endpoint 2: BULK (in) 64 bytes* 2-FIFO
Endpoint 3: Interrupt (in) 8 bytes* 1-FIFO
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Descriptor RAM: 384 bytes
I
2
S bus mode/SIO mode selectable (Master, transmission only)
32-byte FIFO buffer
Supports up to 4096 color for TFT, 256 color, 16, 8, 4 gray levels and B/W for STN
Shift register/built-in RAM LCD driver
Supports 16 M, 64 M, 128 M, 256 M, and up to 512-Mbit SDR (Single Data Rate)-SDRAM
Possible to execute instruction on SDRAM
(10) I
2
S (Inter-IC sound) interface: 1 channel
(11) LCD controller
(12) SDRAM controller: 1 channel
(13) Timer for real-time clock (RTC)
(14) Key-on wakeup (Interrupt key input)
(15) 10-bit AD converter: 4 channels
(16) Touch screen interface
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Available to reduce external components
(17) Watchdog timer
(18) Melody/alarm generator
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Melody: Output of clock 4 to 5461 Hz
Alarm: Output of 8 kinds of alarm pattern and 5 kinds of interval interrupt
Expandable up to 512 Mbytes (3 local area/8 bank method)
Independent bank for each program, read data, write data and LCD display data
9 CPU interrupts:
Software interrupt instruction and illegal instruction
(19) MMU
(20) Interrupts: 50 interrupt
34 internal interrupts: Seven selectable priority levels
7 external interrupts: Seven selectable priority levels (6-edge selectable)
RD
(21) Input/output ports: 82 pins (Except Data bus (16bit), Address bus (24bit) and
(22) NAND flash interface: 2 channels
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Direct NAND flash connection capability
ECC calculation (for SLC- type)
pin)
92CH21-2
2009-06-19
TMP92CH21
(23) Stand-by function
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Three HALT modes: IDLE2 (programmable), IDLE1, STOP
Each pin status programmable for stand-by mode
Clock doubler (PLL) supplies 48 MHz for USB, 36 MHz system-clock for others
Clock gear function: Select high-frequency clock fc to fc/16
RTC (fs
=
32.768 kHz)
VCC
=
3.0 V to 3.6 V (fc max
=
40 MHz)
VCC
=
2.7 V to 3.6 V (fc max
=
27 MHz)
144-pin QFP (LQFP144-P-1616-0.40C)
144-pin chip form is also available. For details, contact your local Toshiba sales
representative.
(24) Triple-clock controller
(25) Operating voltage:
(26) Package:
92CH21-3
2009-06-19
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