NB7N017M
3.3 V SiGe 8‐Bit Dual
Modulus Programmable
Divider/Prescaler with CML
Outputs
Description
The NB7N017M is a high speed 8-bit dual modulus programmable
divider/prescaler with 16 mA CML outputs capable of switching at
input frequencies greater than 3.5 GHz. The CML output structure
contains internal 50
W
source termination resistor to V
CC
. The
device generates 400 mV output amplitude with 50
W
receiver
resistor to V
CC
. This I/O structure enables easy implementation of
the NB7N017M in 50
W
systems.
The differential inputs contain 50
W
termination resistors to VT
pads and all differential inputs accept RSECL, ECL, LVDS,
LVCMOS, LVTTL, and CML.
Internally, the NB7N017M uses a > 3.5 GHz 8-bit programmable
down counter. A select pin, SEL, is used to select between two
words, Pa[0:7] and Pb[0:7], that are stored in REGa and REGb
respectively. Two parallel load pins, PLa and PLb, are used to load
the level triggered programming registers, REGa and REGb,
respectively. A differential clock enable, CE, pin is available.
The NB7N017M offers a differential output, TC. Terminal count
output, TC, goes high for one clock cycle when the counter has
reached the all zeros state. To reduce output phase noise, TC is
retimed with the rising edge triggered latches.
Features
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1
52
QFN−52
MN SUFFIX
CASE 485M−01
MARKING DIAGRAM*
52
1
NB7N
017M
AWLYYWWG
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•
•
•
•
•
•
•
•
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Maximum Input Clock Frequency > 3.5 GHz Typical
Differential CLK Clock Input
Differential CE Clock Enable Input
Differential SEL Word Select Input
50
W
Internal Input and Output Termination Resistors
Differential TC Terminal Count Output
All Outputs 16 mA CML with 50
W
Internal Source Termination
to V
CC
All Single-Ended Control Pins CMOS and PECL/NECL Compatible
Counter Programmed Using One of Two Single-Ended Words,
Pa[0:7] and Pb[0:7], Stored in REGa and REGb
REGa and REGb Implemented with Level Triggered Latch
Compatible with Existing 3.3 V LVEP, EP, and SG Devices
Ability to Program the Divider without Disturbing Current Settings
Positive CML Output Operating Range:
♦
V
CC
= 3.0 V to 3.465 V with V
EE
= 0 V
Negative CML Output Operating Range:
♦
V
CC
= 0 V with V
EE
= –3.0 V to –3.465 V
V
BB
Reference Voltage Output
CML Output Level: 400 mV Peak-Peak Output with 50
W
Receiver
Resistor to V
CC
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
1
A
WL
YY
WW
G
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note
AND8002/D.
ORDERING INFORMATION
Device
NB7N017MMNG
NB7N017MMNR2G
Package
QFN−52
(Pb-Free)
QFN−52
(Pb-Free)
Shipping
†
260 Tray JEDEC
2000/Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure,
BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
August, 2016
−
Rev. 5
Publication Order Number:
NB7N017M/D
NB7N017M
Table 1. PIN DESCRIPTION
Pin Name
CLK
CE
MR
I/O
ECL, CML, LVCMOS,
LVDS, LVTTL Input
ECL, CML, LVCMOS,
LVDS, LVTTL Input
CMOS, ECL Input
Default
State
−
−
Low
Single/Differential
(Notes 1 and 2)
Differential
Differential
Single
Clock
Clock Enable
Asynchronous Master Reset: Counter set to 0000 0000 to
reload at next CLK pulse, REGa and REGb = 1111 1111 and
TC = 1.
Divide Select
Parallel Load Counter Latch from Pa[0:7], Pb[0:7] (Level
Triggered)
Terminal Count, 16 mA CML output with 50
W
Source
Termination to V
CC
(Note 5)
Counter Program Pins. CMOS and PECL/NECL compatible
Pa7 = MSB, Pb7 = MSB
Positive Supply
Negative Supply
50
W
Internal Input Termination Resistor (Note 6)
Description
SEL
PLa, PLb
TC
Pa[0:7], Pb[0:7]
V
CC
V
EE
VTCLK, VTCLK,
VTSEL, VTSEL
VTCE, VTCE
V
BB
NC
EP
ECL, CML, LVCMOS,
LVDS, LVTTL Input
CMOS, ECL Input
CML Output
CMOS, ECL Input
Power
Power
Termination
−
Low
−
High
−
Differential
Single
Differential
Single
−
−
Differential
−
−
Output
N/A
−
−
−
−
−
CMOS/ECL Reference Voltage Output
No Connect (Note 4)
Exposed Pad (Note 3)
−
−
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1. All high speed inputs and outputs are differential to improve performance.
2. All single-ended inputs are CMOS and NECL/ECL compatible.
3. All V
CC
and V
EE
pins must be externally connected to external power supply voltage to guarantee proper device operation. The thermally
exposed pad (EP) on package bottom (see case drawing) must be attached to a heat-sinking conduit. Exposed pad is bonded to the lowest
voltage potential, V
EE
.
4. The NC pins are electrically connected to the die and must be left open.
5. CML outputs require 50
W
receiver termination resistor to V
CC
for proper operation.
6. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied
then the device will be susceptible to self-oscillation.
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