FemtoClock™ Crystal-to-LVDS
Clock Generator
ICS844251I-15
DATA SHEET
General Description
The ICS844251I-15 is an Ethernet Clock Generator
and a member of the HiPerClocks
®
family of high
HiPerClockS™
performance devices from IDT. The ICS844251I-15
uses an 18pF parallel resonant crystal over the range
of 23.2MHz - 30MHz. For Ethernet applications, a
25MHz crystal is used. The device has excellent <1ps phase jitter
performance, over the 1.875MHz - 20MHz integration range. The
ICS844251I-15 is packaged in a small 8-pin TSSOP, making it ideal
for use in systems with limited board space.
Features
•
•
•
•
•
•
•
•
One differential LVDS output pair
Crystal oscillator interface designed for 18pF, parallel resonant
crystal (23.2MHz – 30MHz)
Output frequency ranges: 116MHz – 150MHz and
580MHz – 750MHz
VCO range: 580MHz – 750MHz
RMS phase jitter at 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.46ps (typical)
Full 2.5V output supply mode
-40°C to 85°C ambient operating temperature
Available in a lead-free (RoHS 6) package
ICS
Common Configuration Table
Inputs
Crystal Frequency (MHz)
25
26.667
25 (default)
26.667
FREQ_SEL
1
1
0
0
M
25
25
25
25
N
1
1
5
5
Multiplication Value M/N
25
25
5
5
Output Frequency Range
(MHz)
625
666.67
125
133.33
Block Diagram
FREQ_SEL
Pulldown
Pin Assignment
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
nQ
FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
580MHz - 750MHz
FREQ_SEL N
0
(default)
÷5
1
÷1
Q
nQ
M = ÷25
(fixed)
ICS844251I-15
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
ICS844251BGI-15 REVISION A SEPTEMBER 18, 2009
1
©2009 Integrated Device Technology, Inc.
ICS844251I-15 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1
2
3,
4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT
XTAL_IN
FREQ_SEL
nQ, Q
V
DD
Power
Power
Input
Input
Output
Power
Pulldown
Type
Description
Analog supply pin.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Frequency select pin. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Core supply pin.
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Ω
ICS844251BGI-15 REVISION A SEPTEMBER 18, 2009
2
©2009 Integrated Device Technology, Inc.
ICS844251I-15 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
129.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.10
Typical
2.5
2.5
Maximum
2.625
V
DD
95
10
Units
V
V
mA
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-5
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
Units
V
V
µA
µA
Table 3C. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.0
Test Conditions
Minimum
247
Typical
Maximum
454
50
1.4
50
Units
mV
mV
V
mV
ICS844251BGI-15 REVISION A SEPTEMBER 18, 2009
3
©2009 Integrated Device Technology, Inc.
ICS844251I-15 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
23.2
Test Conditions
Minimum
Typical
Fundamental
30
50
7
MHz
Maximum
Units
Ω
pF
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
Parameter
Output Frequency
Test Conditions
FREQ_SEL = 0
FREQ_SEL = 1
125MHz,
Integration Range: 1.875MHz – 20MHz
625MHz,
Integration Range: 1.875MHz – 20MHz
20% to 80%
FREQ_SEL = 0
FREQ_SEL = 1
70
48
46
Minimum
116
580
0.46
0.35
550
52
54
Typical
Maximum
150
750
Units
MHz
MHz
ps
ps
ps
%
%
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
t
R
/ t
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to Phase Noise Plots.
ICS844251BGI-15 REVISION A SEPTEMBER 18, 2009
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©2009 Integrated Device Technology, Inc.
ICS844251I-15 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Typical Phase Noise at 125MHz
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.46ps (typical)
dBc
Hz
Noise Power
Raw Phase Noise Data
Offset Frequency (Hz)
ICS844251BGI-15 REVISION A SEPTEMBER 18, 2009
5
➝
Phase Noise Result by adding a
Ethernet filter to raw data
➝
Ethernet Filter
➝
©2009 Integrated Device Technology, Inc.
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