74ACT299
8 BIT PIPO SHIFT REGISTER
WITH ASYNCHRONOUS CLEAR
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DESCRIPTION
The 74ACT299 is an advanced high-speed CMOS
8-BIT PIPO
SHIFT REGISTER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
These devices have four modes (HOLD, SHIFT
LEFT, SHIFT RIGHT and LOAD DATA). Each
mode is chosen by two function select inputs (S0,
S1) as shown in the Truth Table. When one or
PIN CONNECTION AND IEC LOGIC SYMBOLS
s
HIGH SPEED:
f
MAX
= 240MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 8µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 299
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
b
O
both enable inputs, (G1, G2) are high, the eight
input/output terminals are in the high-impedance
state; however sequential operation or clearing of
the register is not affected. Clear function is
asynchronousto clock.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
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74ACT299B
74ACT299M
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74ACT299MTR
74ACT299TTR
April 2001
1/13
74ACT299
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1, 19
2, 3
7, 13, 6, 14, 5, 15, 4, 16
8, 17
9
11
12
18
10
20
SYMBOL
S0, S1
G1, G2
A/QA to H/QH
QA’ to QH’
CLEAR
SR
CLOCK
SL
GND
V
CC
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TRUTH TABLE
INPUTS
MODE
CLEAR
L
L
L
H
H
H
H
H
H
FUNCTION
SELECTED
S1
H
L
X
L
L
L
OUTPUT
CONTROL
CLOCK
X
X
X
X
S0
H
X
L
L
H
H
L
L
H
G1*
X
L
L
L
L
L
L
L
X
G2*
X
L
L
L
L
L
L
Z
CLEAR
HOLD
SHIFT
RIGHT
SHIFT
LEFT
LOAD
X
X
X
X
X
X
L
X
H
H
H
H
L
X
Mode Select Inputs
3-State Output Enable Inputs (Active LOW)
Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver)
Serial Outputs (Standard Output)
Asyncrhronous Master Reset Input (Active LOW)
Serial Data Shift Right Input
Clock Input (LOW to HIGH, Edge-triggered)
Serial Data Shift Left Input
Ground (0V)
Positive Supply Voltage
b
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NAME AND FUNCTION
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INPUTS/OUTPUTS
OUTPUTS
SERIAL
A/QA
SR
X
X
X
X
H
L
X
X
X
Z
L
L
QA0
H
L
QBn
QBn
a
Z
L
L
QH0
QGn
QGn
H
L
h
L
L
L
QA0
H
L
QBn
QBn
a
L
L
L
QH0
QGn
QGn
H
L
h
H/QH
QA’
QH’
SL
* : When one or both controls are high, the eight input/output terminals are the high impedance state: howewer sequential operation or cleanig
of the register is not affected.
Z : High Impedance
Qn0 : The level of An before the indicated steady state input conditions were established.
Qnn : The level of Qn before the most recent active transition indicated by OR
a, h : The level of the steadystate inputs A, H, respectively.
X : Don’t Care
2/13
74ACT299
TIMING CHART
)-
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ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
O
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Current
I
OK
DC Output Diode Current
I
CC
or I
GND
DC V
CC
or Ground Current
T
stg
Storage Temperature
T
L
Lead Temperature (10 sec)
b
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Value
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Unit
V
V
V
mA
mA
mA
mA
°C
°C
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
400
-65 to +150
300
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Parameter
Value
4.5 to 5.5
0 to V
CC
0 to V
CC
-55 to 125
8
Unit
V
V
V
°C
ns/V
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
1) V
IN
from 0.8V to 2.0V
4/13
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